rate_adjust.tan.qmsg

VerilogHDL开发

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Aug 04 17:17:09 2006 " "Info: Processing started: Fri Aug 04 17:17:09 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off Rate_Adjust -c Rate_Adjust " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off Rate_Adjust -c Rate_Adjust" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "Rate_Data\[8\] Rate_Adjust_Out 9.600 ns Longest " "Info: Longest tpd from source pin \"Rate_Data\[8\]\" to destination pin \"Rate_Adjust_Out\" is 9.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns Rate_Data\[8\] 1 PIN PIN_29 1 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_29; Fanout = 1; PIN Node = 'Rate_Data\[8\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Rate_Adjust/db/Rate_Adjust_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Rate_Adjust/db/Rate_Adjust_cmp.qrpt" Compiler "Rate_Adjust" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Rate_Adjust/db/Rate_Adjust.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Rate_Adjust/" "" "" { Rate_Data[8] } "NODE_NAME" } "" } } { "Rate_Adjust.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Rate_Adjust/Rate_Adjust.v" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(3.500 ns) 4.800 ns always0~163 2 COMB LC9 1 " "Info: 2: + IC(1.100 ns) + CELL(3.500 ns) = 4.800 ns; Loc. = LC9; Fanout = 1; COMB Node = 'always0~163'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Rate_Adjust/db/Rate_Adjust_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Rate_Adjust/db/Rate_Adjust_cmp.qrpt" Compiler "Rate_Adjust" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Rate_Adjust/db/Rate_Adjust.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Rate_Adjust/" "" "4.600 ns" { Rate_Data[8] always0~163 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(3.500 ns) 9.400 ns Rate_Adjust_Out~10 3 COMB LC33 1 " "Info: 3: + IC(1.100 ns) + CELL(3.500 ns) = 9.400 ns; Loc. = LC33; Fanout = 1; COMB Node = 'Rate_Adjust_Out~10'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Rate_Adjust/db/Rate_Adjust_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Rate_Adjust/db/Rate_Adjust_cmp.qrpt" Compiler "Rate_Adjust" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Rate_Adjust/db/Rate_Adjust.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Rate_Adjust/" "" "4.600 ns" { always0~163 Rate_Adjust_Out~10 } "NODE_NAME" } "" } } { "Rate_Adjust.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Rate_Adjust/Rate_Adjust.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 9.600 ns Rate_Adjust_Out 4 PIN PIN_40 0 " "Info: 4: + IC(0.000 ns) + CELL(0.200 ns) = 9.600 ns; Loc. = PIN_40; Fanout = 0; PIN Node = 'Rate_Adjust_Out'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Rate_Adjust/db/Rate_Adjust_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Rate_Adjust/db/Rate_Adjust_cmp.qrpt" Compiler "Rate_Adjust" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Rate_Adjust/db/Rate_Adjust.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Rate_Adjust/" "" "0.200 ns" { Rate_Adjust_Out~10 Rate_Adjust_Out } "NODE_NAME" } "" } } { "Rate_Adjust.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Rate_Adjust/Rate_Adjust.v" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.400 ns 77.08 % " "Info: Total cell delay = 7.400 ns ( 77.08 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.200 ns 22.92 % " "Info: Total interconnect delay = 2.200 ns ( 22.92 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Rate_Adjust/db/Rate_Adjust_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Rate_Adjust/db/Rate_Adjust_cmp.qrpt" Compiler "Rate_Adjust" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Rate_Adjust/db/Rate_Adjust.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Rate_Adjust/" "" "9.600 ns" { Rate_Data[8] always0~163 Rate_Adjust_Out~10 Rate_Adjust_Out } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "9.600 ns" { Rate_Data[8] Rate_Data[8]~out always0~163 Rate_Adjust_Out~10 Rate_Adjust_Out } { 0.000ns 0.000ns 1.100ns 1.100ns 0.000ns } { 0.000ns 0.200ns 3.500ns 3.500ns 0.200ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Aug 04 17:17:09 2006 " "Info: Processing ended: Fri Aug 04 17:17:09 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}