rate_adjust.fit.summary

VerilogHDL开发

Flow Status : Successful - Fri Aug 04 17:17:03 2006
Quartus II Version : 4.2 Build 157 12/07/2004 SJ Full Version
Revision Name : Rate_Adjust
Top-level Entity Name : Rate_Adjust
Family : MAX7000S
Met timing requirements : N/A
Total macrocells : 9 / 64 ( 14 % )
Total pins : 40 / 68 ( 58 % )
Device : EPM7064STC100-5
Timing Models : Final