rate_adjust.v

VerilogHDL开发

module Rate_Adjust(
						En,
						Reset,
						Rate_Adjust_Select,
						Rate_Data,
						Rate_Set,
						Rate_Adjust_Out
						);
input  En;
input  Reset;
input  Rate_Adjust_Select;
input  [15:0] Rate_Data;
input  [15:0] Rate_Set;
output Rate_Adjust_Out;

reg Rate_Adjust_Out;

always @(En or Reset or Rate_Adjust_Select or Rate_Data or Rate_Set)
begin
  if((En == 1'b1) || (Reset == 1'b1) ||(Rate_Adjust_Select == 1'b0))
	Rate_Adjust_Out <= 1'b0;
  else
  begin
    if(Rate_Data == Rate_Set)
      Rate_Adjust_Out <= 1'b0;
    else
      Rate_Adjust_Out <= 1'b1;   
  end
end

endmodule