eeprom.sim.qmsg

eeprom的Verilog HDL源代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Simulator Quartus II " "Info: Running Quartus II Simulator" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Nov 04 10:08:06 2007 " "Info: Processing started: Sun Nov 04 10:08:06 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sim --read_settings_files=on --write_settings_files=off eeprom -c eeprom " "Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off eeprom -c eeprom" {  } {  } 0}
{ "Info" "ISIM_OVERWRITE_WAVEFORM_INPUTS_WITH_SIMULATION_OUTPUTS" "" "Info: Overwriting simulation input file with simulation results" {  } {  } 0}
{ "Warning" "WSIM_WRONG_IO_TYPE_CHANNEL" "sda~result Output Buried " "Warning: Wrong node type for node \"sda~result\" in vector source file. Design node is of type Output, but signal in vector source file is of type Buried" {  } {  } 0}
{ "Warning" "WSIM_WRONG_IO_TYPE_CHANNEL" "data\[0\]~result Output Buried " "Warning: Wrong node type for node \"data\[0\]~result\" in vector source file. Design node is of type Output, but signal in vector source file is of type Buried" {  } {  } 0}
{ "Warning" "WSIM_WRONG_IO_TYPE_CHANNEL" "data\[1\]~result Output Buried " "Warning: Wrong node type for node \"data\[1\]~result\" in vector source file. Design node is of type Output, but signal in vector source file is of type Buried" {  } {  } 0}
{ "Warning" "WSIM_WRONG_IO_TYPE_CHANNEL" "data\[2\]~result Output Buried " "Warning: Wrong node type for node \"data\[2\]~result\" in vector source file. Design node is of type Output, but signal in vector source file is of type Buried" {  } {  } 0}
{ "Warning" "WSIM_WRONG_IO_TYPE_CHANNEL" "data\[3\]~result Output Buried " "Warning: Wrong node type for node \"data\[3\]~result\" in vector source file. Design node is of type Output, but signal in vector source file is of type Buried" {  } {  } 0}
{ "Warning" "WSIM_WRONG_IO_TYPE_CHANNEL" "data\[4\]~result Output Buried " "Warning: Wrong node type for node \"data\[4\]~result\" in vector source file. Design node is of type Output, but signal in vector source file is of type Buried" {  } {  } 0}
{ "Warning" "WSIM_WRONG_IO_TYPE_CHANNEL" "data\[5\]~result Output Buried " "Warning: Wrong node type for node \"data\[5\]~result\" in vector source file. Design node is of type Output, but signal in vector source file is of type Buried" {  } {  } 0}
{ "Warning" "WSIM_WRONG_IO_TYPE_CHANNEL" "data\[6\]~result Output Buried " "Warning: Wrong node type for node \"data\[6\]~result\" in vector source file. Design node is of type Output, but signal in vector source file is of type Buried" {  } {  } 0}
{ "Warning" "WSIM_WRONG_IO_TYPE_CHANNEL" "data\[7\]~result Output Buried " "Warning: Wrong node type for node \"data\[7\]~result\" in vector source file. Design node is of type Output, but signal in vector source file is of type Buried" {  } {  } 0}
{ "Warning" "WSDB_CLOCK_SENSITIVE_CHANGE" "\|eeprom\|data_from_rm\[7\] 81.25 us " "Warning: Found clock-sensitive change during active clock edge at time 81.25 us on register \"\|eeprom\|data_from_rm\[7\]\"" {  } {  } 0}
{ "Warning" "WSDB_CLOCK_SENSITIVE_CHANGE" "\|eeprom\|data_from_rm\[6\] 81.25 us " "Warning: Found clock-sensitive change during active clock edge at time 81.25 us on register \"\|eeprom\|data_from_rm\[6\]\"" {  } {  } 0}
{ "Warning" "WSDB_CLOCK_SENSITIVE_CHANGE" "\|eeprom\|data_from_rm\[5\] 81.25 us " "Warning: Found clock-sensitive change during active clock edge at time 81.25 us on register \"\|eeprom\|data_from_rm\[5\]\"" {  } {  } 0}
{ "Warning" "WSDB_CLOCK_SENSITIVE_CHANGE" "\|eeprom\|data_from_rm\[4\] 81.25 us " "Warning: Found clock-sensitive change during active clock edge at time 81.25 us on register \"\|eeprom\|data_from_rm\[4\]\"" {  } {  } 0}
{ "Warning" "WSDB_CLOCK_SENSITIVE_CHANGE" "\|eeprom\|data_from_rm\[3\] 81.25 us " "Warning: Found clock-sensitive change during active clock edge at time 81.25 us on register \"\|eeprom\|data_from_rm\[3\]\"" {  } {  } 0}
{ "Warning" "WSDB_CLOCK_SENSITIVE_CHANGE" "\|eeprom\|data_from_rm\[2\] 81.25 us " "Warning: Found clock-sensitive change during active clock edge at time 81.25 us on register \"\|eeprom\|data_from_rm\[2\]\"" {  } {  } 0}
{ "Warning" "WSDB_CLOCK_SENSITIVE_CHANGE" "\|eeprom\|data_from_rm\[1\] 81.25 us " "Warning: Found clock-sensitive change during active clock edge at time 81.25 us on register \"\|eeprom\|data_from_rm\[1\]\"" {  } {  } 0}
{ "Warning" "WSDB_CLOCK_SENSITIVE_CHANGE" "\|eeprom\|data_from_rm\[0\] 81.25 us " "Warning: Found clock-sensitive change during active clock edge at time 81.25 us on register \"\|eeprom\|data_from_rm\[0\]\"" {  } {  } 0}
{ "Info" "ISIM_SIM_SIMULATION_COVERAGE" "     78.57 % " "Info: Simulation coverage is      78.57 %" {  } {  } 0}
{ "Info" "ISIM_SIM_NUMBER_OF_TRANSITION" "15113 " "Info: Number of transitions in simulation is 15113" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Simulator 0 s 17 s Quartus II " "Info: Quartus II Simulator was successful. 0 errors, 17 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Nov 04 10:08:06 2007 " "Info: Processing ended: Sun Nov 04 10:08:06 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}