eeprom.smp_dump.txt

eeprom的Verilog HDL源代码

State Machine - |eeprom|sh8out_state
Name sh8out_state.sh8out_end sh8out_state.sh8out_bit0 sh8out_state.sh8out_bit1 sh8out_state.sh8out_bit2 sh8out_state.sh8out_bit3 sh8out_state.sh8out_bit4 sh8out_state.sh8out_bit5 sh8out_state.sh8out_bit6 sh8out_state.sh8out_bit7 
sh8out_state.sh8out_end 0 0 0 0 0 0 0 0 0 
sh8out_state.sh8out_bit0 1 1 0 0 0 0 0 0 0 
sh8out_state.sh8out_bit1 1 0 1 0 0 0 0 0 0 
sh8out_state.sh8out_bit2 1 0 0 1 0 0 0 0 0 
sh8out_state.sh8out_bit3 1 0 0 0 1 0 0 0 0 
sh8out_state.sh8out_bit4 1 0 0 0 0 1 0 0 0 
sh8out_state.sh8out_bit5 1 0 0 0 0 0 1 0 0 
sh8out_state.sh8out_bit7 1 0 0 0 0 0 0 0 1 
sh8out_state.sh8out_bit6 1 0 0 0 0 0 0 1 0 

State Machine - |eeprom|stop_state
Name stop_state.stop_end stop_state.stop_bit stop_state.stop_begin 
stop_state.stop_end 0 0 0 
stop_state.stop_bit 1 1 0 
stop_state.stop_begin 1 0 1