eeprom.tan.qmsg

eeprom的Verilog HDL源代码

{ "Info" "ITDB_FULL_TCO_RESULT" "clk sda sh8out_buf\[7\]~reg0 19.400 ns register " "Info: tco from clock \"clk\" to destination pin \"sda\" through register \"sh8out_buf\[7\]~reg0\" is 19.400 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.400 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_55 66 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 66; CLK Node = 'clk'" {  } { { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "" { clk } "NODE_NAME" } "" } } { "eeprom.v" "" { Text "D:/eeprom/eeprom.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns sh8out_buf\[7\]~reg0 2 REG LC6_E14 3 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC6_E14; Fanout = 3; REG Node = 'sh8out_buf\[7\]~reg0'" {  } { { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "0.400 ns" { clk sh8out_buf[7]~reg0 } "NODE_NAME" } "" } } { "eeprom.v" "" { Text "D:/eeprom/eeprom.v" 73 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "2.400 ns" { clk sh8out_buf[7]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out sh8out_buf[7]~reg0 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "eeprom.v" "" { Text "D:/eeprom/eeprom.v" 73 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "16.500 ns + Longest register pin " "Info: + Longest register to pin delay is 16.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sh8out_buf\[7\]~reg0 1 REG LC6_E14 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_E14; Fanout = 3; REG Node = 'sh8out_buf\[7\]~reg0'" {  } { { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "" { sh8out_buf[7]~reg0 } "NODE_NAME" } "" } } { "eeprom.v" "" { Text "D:/eeprom/eeprom.v" 73 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(1.600 ns) 3.600 ns sda4~7 2 COMB LC6_E36 1 " "Info: 2: + IC(2.000 ns) + CELL(1.600 ns) = 3.600 ns; Loc. = LC6_E36; Fanout = 1; COMB Node = 'sda4~7'" {  } { { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "3.600 ns" { sh8out_buf[7]~reg0 sda4~7 } "NODE_NAME" } "" } } { "eeprom.v" "" { Text "D:/eeprom/eeprom.v" 20 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(1.400 ns) 7.300 ns sda4 3 COMB LC1_E5 1 " "Info: 3: + IC(2.300 ns) + CELL(1.400 ns) = 7.300 ns; Loc. = LC1_E5; Fanout = 1; COMB Node = 'sda4'" {  } { { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "3.700 ns" { sda4~7 sda4 } "NODE_NAME" } "" } } { "eeprom.v" "" { Text "D:/eeprom/eeprom.v" 20 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(6.300 ns) 16.500 ns sda 4 PIN PIN_11 0 " "Info: 4: + IC(2.900 ns) + CELL(6.300 ns) = 16.500 ns; Loc. = PIN_11; Fanout = 0; PIN Node = 'sda'" {  } { { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "9.200 ns" { sda4 sda } "NODE_NAME" } "" } } { "eeprom.v" "" { Text "D:/eeprom/eeprom.v" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.300 ns 56.36 % " "Info: Total cell delay = 9.300 ns ( 56.36 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.200 ns 43.64 % " "Info: Total interconnect delay = 7.200 ns ( 43.64 % )" {  } {  } 0}  } { { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "16.500 ns" { sh8out_buf[7]~reg0 sda4~7 sda4 sda } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "16.500 ns" { sh8out_buf[7]~reg0 sda4~7 sda4 sda } { 0.000ns 2.000ns 2.300ns 2.900ns } { 0.000ns 1.600ns 1.400ns 6.300ns } } }  } 0}  } { { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "2.400 ns" { clk sh8out_buf[7]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out sh8out_buf[7]~reg0 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "16.500 ns" { sh8out_buf[7]~reg0 sda4~7 sda4 sda } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "16.500 ns" { sh8out_buf[7]~reg0 sda4~7 sda4 sda } { 0.000ns 2.000ns 2.300ns 2.900ns } { 0.000ns 1.600ns 1.400ns 6.300ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "scl~reg0 reset clk 0.500 ns register " "Info: th for register \"scl~reg0\" (data pin = \"reset\", clock pin = \"clk\") is 0.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.400 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_55 66 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 66; CLK Node = 'clk'" {  } { { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "" { clk } "NODE_NAME" } "" } } { "eeprom.v" "" { Text "D:/eeprom/eeprom.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns scl~reg0 2 REG LC1_E8 43 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC1_E8; Fanout = 43; REG Node = 'scl~reg0'" {  } { { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "0.400 ns" { clk scl~reg0 } "NODE_NAME" } "" } } { "eeprom.v" "" { Text "D:/eeprom/eeprom.v" 68 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "2.400 ns" { clk scl~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out scl~reg0 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" {  } { { "eeprom.v" "" { Text "D:/eeprom/eeprom.v" 68 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.200 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns reset 1 PIN PIN_126 46 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 46; PIN Node = 'reset'" {  } { { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "" { reset } "NODE_NAME" } "" } } { "eeprom.v" "" { Text "D:/eeprom/eeprom.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.000 ns) 3.200 ns scl~reg0 2 REG LC1_E8 43 " "Info: 2: + IC(0.200 ns) + CELL(1.000 ns) = 3.200 ns; Loc. = LC1_E8; Fanout = 43; REG Node = 'scl~reg0'" {  } { { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "1.200 ns" { reset scl~reg0 } "NODE_NAME" } "" } } { "eeprom.v" "" { Text "D:/eeprom/eeprom.v" 68 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 93.75 % " "Info: Total cell delay = 3.000 ns ( 93.75 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns 6.25 % " "Info: Total interconnect delay = 0.200 ns ( 6.25 % )" {  } {  } 0}  } { { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "3.200 ns" { reset scl~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.200 ns" { reset reset~out scl~reg0 } { 0.000ns 0.000ns 0.200ns } { 0.000ns 2.000ns 1.000ns } } }  } 0}  } { { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "2.400 ns" { clk scl~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out scl~reg0 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "3.200 ns" { reset scl~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.200 ns" { reset reset~out scl~reg0 } { 0.000ns 0.000ns 0.200ns } { 0.000ns 2.000ns 1.000ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Nov 04 09:56:02 2007 " "Info: Processing ended: Sun Nov 04 09:56:02 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}