eeprom.tan.qmsg

eeprom的Verilog HDL源代码

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "eeprom.v" "" { Text "D:/eeprom/eeprom.v" 3 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register scl~reg0 register link_sda 34.72 MHz 28.8 ns Internal " "Info: Clock \"clk\" has Internal fmax of 34.72 MHz between source register \"scl~reg0\" and destination register \"link_sda\" (period= 28.8 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.300 ns + Longest register register " "Info: + Longest register to register delay is 13.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns scl~reg0 1 REG LC1_E8 43 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_E8; Fanout = 43; REG Node = 'scl~reg0'" {  } { { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "" { scl~reg0 } "NODE_NAME" } "" } } { "eeprom.v" "" { Text "D:/eeprom/eeprom.v" 68 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(1.600 ns) 4.300 ns Select~13147 2 COMB LC1_E34 4 " "Info: 2: + IC(2.700 ns) + CELL(1.600 ns) = 4.300 ns; Loc. = LC1_E34; Fanout = 4; COMB Node = 'Select~13147'" {  } { { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "4.300 ns" { scl~reg0 Select~13147 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.400 ns) 6.700 ns Select~13162 3 COMB LC3_E35 1 " "Info: 3: + IC(1.000 ns) + CELL(1.400 ns) = 6.700 ns; Loc. = LC3_E35; Fanout = 1; COMB Node = 'Select~13162'" {  } { { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "2.400 ns" { Select~13147 Select~13162 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.600 ns) 8.600 ns Select~13163 4 COMB LC4_E35 1 " "Info: 4: + IC(0.300 ns) + CELL(1.600 ns) = 8.600 ns; Loc. = LC4_E35; Fanout = 1; COMB Node = 'Select~13163'" {  } { { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "1.900 ns" { Select~13162 Select~13163 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.400 ns) 10.300 ns Select~13164 5 COMB LC6_E35 1 " "Info: 5: + IC(0.300 ns) + CELL(1.400 ns) = 10.300 ns; Loc. = LC6_E35; Fanout = 1; COMB Node = 'Select~13164'" {  } { { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "1.700 ns" { Select~13163 Select~13164 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.400 ns) 12.000 ns Select~13165 6 COMB LC7_E35 1 " "Info: 6: + IC(0.300 ns) + CELL(1.400 ns) = 12.000 ns; Loc. = LC7_E35; Fanout = 1; COMB Node = 'Select~13165'" {  } { { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "1.700 ns" { Select~13164 Select~13165 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.000 ns) 13.300 ns link_sda 7 REG LC1_E35 4 " "Info: 7: + IC(0.300 ns) + CELL(1.000 ns) = 13.300 ns; Loc. = LC1_E35; Fanout = 4; REG Node = 'link_sda'" {  } { { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "1.300 ns" { Select~13165 link_sda } "NODE_NAME" } "" } } { "eeprom.v" "" { Text "D:/eeprom/eeprom.v" 19 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.400 ns 63.16 % " "Info: Total cell delay = 8.400 ns ( 63.16 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.900 ns 36.84 % " "Info: Total interconnect delay = 4.900 ns ( 36.84 % )" {  } {  } 0}  } { { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "13.300 ns" { scl~reg0 Select~13147 Select~13162 Select~13163 Select~13164 Select~13165 link_sda } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "13.300 ns" { scl~reg0 Select~13147 Select~13162 Select~13163 Select~13164 Select~13165 link_sda } { 0.000ns 2.700ns 1.000ns 0.300ns 0.300ns 0.300ns 0.300ns } { 0.000ns 1.600ns 1.400ns 1.600ns 1.400ns 1.400ns 1.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.400 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_55 66 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 66; CLK Node = 'clk'" {  } { { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "" { clk } "NODE_NAME" } "" } } { "eeprom.v" "" { Text "D:/eeprom/eeprom.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns link_sda 2 REG LC1_E35 4 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC1_E35; Fanout = 4; REG Node = 'link_sda'" {  } { { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "0.400 ns" { clk link_sda } "NODE_NAME" } "" } } { "eeprom.v" "" { Text "D:/eeprom/eeprom.v" 19 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "2.400 ns" { clk link_sda } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out link_sda } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.400 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_55 66 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 66; CLK Node = 'clk'" {  } { { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "" { clk } "NODE_NAME" } "" } } { "eeprom.v" "" { Text "D:/eeprom/eeprom.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns scl~reg0 2 REG LC1_E8 43 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC1_E8; Fanout = 43; REG Node = 'scl~reg0'" {  } { { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "0.400 ns" { clk scl~reg0 } "NODE_NAME" } "" } } { "eeprom.v" "" { Text "D:/eeprom/eeprom.v" 68 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "2.400 ns" { clk scl~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out scl~reg0 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0}  } { { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "2.400 ns" { clk link_sda } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out link_sda } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "2.400 ns" { clk scl~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out scl~reg0 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "eeprom.v" "" { Text "D:/eeprom/eeprom.v" 68 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "eeprom.v" "" { Text "D:/eeprom/eeprom.v" 19 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "eeprom.v" "" { Text "D:/eeprom/eeprom.v" 68 -1 0 } } { "eeprom.v" "" { Text "D:/eeprom/eeprom.v" 19 -1 0 } }  } 0}  } { { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "13.300 ns" { scl~reg0 Select~13147 Select~13162 Select~13163 Select~13164 Select~13165 link_sda } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "13.300 ns" { scl~reg0 Select~13147 Select~13162 Select~13163 Select~13164 Select~13165 link_sda } { 0.000ns 2.700ns 1.000ns 0.300ns 0.300ns 0.300ns 0.300ns } { 0.000ns 1.600ns 1.400ns 1.600ns 1.400ns 1.400ns 1.000ns } } } { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "2.400 ns" { clk link_sda } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out link_sda } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "2.400 ns" { clk scl~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out scl~reg0 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "sh8out_buf\[1\]~reg0 data\[1\] clk 15.700 ns register " "Info: tsu for register \"sh8out_buf\[1\]~reg0\" (data pin = \"data\[1\]\", clock pin = \"clk\") is 15.700 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "17.500 ns + Longest pin register " "Info: + Longest pin to register delay is 17.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns data\[1\] 1 PIN PIN_8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_8; Fanout = 1; PIN Node = 'data\[1\]'" {  } { { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "" { data[1] } "NODE_NAME" } "" } } { "eeprom.v" "" { Text "D:/eeprom/eeprom.v" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns data\[1\]~6 2 COMB IOC_8 1 " "Info: 2: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = IOC_8; Fanout = 1; COMB Node = 'data\[1\]~6'" {  } { { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "4.900 ns" { data[1] data[1]~6 } "NODE_NAME" } "" } } { "eeprom.v" "" { Text "D:/eeprom/eeprom.v" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.400 ns) 8.800 ns Select~13070 3 COMB LC1_A6 1 " "Info: 3: + IC(2.500 ns) + CELL(1.400 ns) = 8.800 ns; Loc. = LC1_A6; Fanout = 1; COMB Node = 'Select~13070'" {  } { { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "3.900 ns" { data[1]~6 Select~13070 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.400 ns) 11.200 ns Select~13071 4 COMB LC4_A3 1 " "Info: 4: + IC(1.000 ns) + CELL(1.400 ns) = 11.200 ns; Loc. = LC4_A3; Fanout = 1; COMB Node = 'Select~13071'" {  } { { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "2.400 ns" { Select~13070 Select~13071 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.400 ns) 12.900 ns Select~13074 5 COMB LC5_A3 1 " "Info: 5: + IC(0.300 ns) + CELL(1.400 ns) = 12.900 ns; Loc. = LC5_A3; Fanout = 1; COMB Node = 'Select~13074'" {  } { { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "1.700 ns" { Select~13071 Select~13074 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.400 ns) 14.600 ns Select~13077 6 COMB LC1_A3 1 " "Info: 6: + IC(0.300 ns) + CELL(1.400 ns) = 14.600 ns; Loc. = LC1_A3; Fanout = 1; COMB Node = 'Select~13077'" {  } { { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "1.700 ns" { Select~13074 Select~13077 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(1.000 ns) 17.500 ns sh8out_buf\[1\]~reg0 7 REG LC1_E2 6 " "Info: 7: + IC(1.900 ns) + CELL(1.000 ns) = 17.500 ns; Loc. = LC1_E2; Fanout = 6; REG Node = 'sh8out_buf\[1\]~reg0'" {  } { { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "2.900 ns" { Select~13077 sh8out_buf[1]~reg0 } "NODE_NAME" } "" } } { "eeprom.v" "" { Text "D:/eeprom/eeprom.v" 73 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.500 ns 65.71 % " "Info: Total cell delay = 11.500 ns ( 65.71 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.000 ns 34.29 % " "Info: Total interconnect delay = 6.000 ns ( 34.29 % )" {  } {  } 0}  } { { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "17.500 ns" { data[1] data[1]~6 Select~13070 Select~13071 Select~13074 Select~13077 sh8out_buf[1]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "17.500 ns" { data[1] data[1]~6 Select~13070 Select~13071 Select~13074 Select~13077 sh8out_buf[1]~reg0 } { 0.000ns 0.000ns 2.500ns 1.000ns 0.300ns 0.300ns 1.900ns } { 0.000ns 4.900ns 1.400ns 1.400ns 1.400ns 1.400ns 1.000ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "eeprom.v" "" { Text "D:/eeprom/eeprom.v" 73 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.400 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_55 66 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 66; CLK Node = 'clk'" {  } { { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "" { clk } "NODE_NAME" } "" } } { "eeprom.v" "" { Text "D:/eeprom/eeprom.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns sh8out_buf\[1\]~reg0 2 REG LC1_E2 6 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC1_E2; Fanout = 6; REG Node = 'sh8out_buf\[1\]~reg0'" {  } { { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "0.400 ns" { clk sh8out_buf[1]~reg0 } "NODE_NAME" } "" } } { "eeprom.v" "" { Text "D:/eeprom/eeprom.v" 73 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "2.400 ns" { clk sh8out_buf[1]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out sh8out_buf[1]~reg0 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0}  } { { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "17.500 ns" { data[1] data[1]~6 Select~13070 Select~13071 Select~13074 Select~13077 sh8out_buf[1]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "17.500 ns" { data[1] data[1]~6 Select~13070 Select~13071 Select~13074 Select~13077 sh8out_buf[1]~reg0 } { 0.000ns 0.000ns 2.500ns 1.000ns 0.300ns 0.300ns 1.900ns } { 0.000ns 4.900ns 1.400ns 1.400ns 1.400ns 1.400ns 1.000ns } } } { "D:/eeprom/db/eeprom_cmp.qrpt" "" { Report "D:/eeprom/db/eeprom_cmp.qrpt" Compiler "eeprom" "UNKNOWN" "V1" "D:/eeprom/db/eeprom.quartus_db" { Floorplan "D:/eeprom/" "" "2.400 ns" { clk sh8out_buf[1]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out sh8out_buf[1]~reg0 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0}