eeprom.fit.summary

eeprom的Verilog HDL源代码

Flow Status : Successful - Sun Nov 04 09:55:56 2007
Quartus II Version : 5.0 Build 168 06/22/2005 SP 1 SJ Full Version
Revision Name : eeprom
Top-level Entity Name : eeprom
Family : ACEX1K
Device : EP1K30TC144-3
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 363 / 1,728 ( 21 % )
Total pins : 58 / 102 ( 56 % )
Total memory bits : 0 / 24,576 ( 0 % )
Total PLLs : 0