fsm.v

来自「检测输入数据中的“10110”序列」· Verilog 代码 · 共 43 行

module	fsm(iclk,rst_,din,catch,overflow);
	input	iclk,rst_,din;
	output  [3:0] catch;
	reg		[3:0] catch;
	output	overflow;
	reg		overflow;
	reg		[2:0]	state;
	parameter	IDLE='d0,A='d1,B='d2,
				 C='d3,D='d4,E='d5;

always @ (posedge iclk or negedge rst_)
	if(!rst_)
		begin
		state<=IDLE;
		overflow<=0;
		catch<=0;
		end
	else
	begin
	if(!overflow)
	case(state)
		IDLE:	if(din==1)	state<=A;
		A:	if(din==0)	state<=B;
			else		state<=A;
		B:	if(din==1)	state<=C;
			else		state<=IDLE;
		C:	if(din==1)	state<=D;
			else		state<=B;
		D:	if(din==0)	
			begin
			state<=E;
			catch<=catch+1;
			if(catch==15) overflow<=1;
			end
			else		state<=A;
		E:	if(din==1)	state<=C;
			else		state<=IDLE;
		default:state<=IDLE;
	endcase
	end
endmodule