ads7844.map.rpt

本源码介绍了ADS7844 AD转换芯片的VHDL控制器。

; inst4/inst/101 ; Stuck at GND              ; inst4/inst/100                         ;
;                ; due to stuck port data_in ;                                        ;
+----------------+---------------------------+----------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 33    ;
; Number of registers using Synchronous Clear  ; 5     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 25    ;
; Number of registers using Asynchronous Load  ; 5     ;
; Number of registers using Clock Enable       ; 9     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------+
; Source assignments for d_latch:inst6|altsyncram0:inst33|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated ;
+---------------------------------+--------------------+------+----------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                       ;
+---------------------------------+--------------------+------+----------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                        ;
+---------------------------------+--------------------+------+----------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------+
; Source assignments for d_latch:inst6|altsyncram0:inst34|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated ;
+---------------------------------+--------------------+------+----------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                       ;
+---------------------------------+--------------------+------+----------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                        ;
+---------------------------------+--------------------+------+----------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------+
; Source assignments for d_latch:inst6|altsyncram0:inst31|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated ;
+---------------------------------+--------------------+------+----------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                       ;
+---------------------------------+--------------------+------+----------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                        ;
+---------------------------------+--------------------+------+----------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------+
; Source assignments for d_latch:inst6|altsyncram0:inst32|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated ;
+---------------------------------+--------------------+------+----------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                       ;
+---------------------------------+--------------------+------+----------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                        ;
+---------------------------------+--------------------+------+----------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------+
; Source assignments for d_latch:inst6|altsyncram0:inst29|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated ;
+---------------------------------+--------------------+------+----------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                       ;
+---------------------------------+--------------------+------+----------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                        ;
+---------------------------------+--------------------+------+----------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------+
; Source assignments for d_latch:inst6|altsyncram0:inst30|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated ;
+---------------------------------+--------------------+------+----------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                       ;
+---------------------------------+--------------------+------+----------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                        ;
+---------------------------------+--------------------+------+----------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------+
; Source assignments for d_latch:inst6|altsyncram0:inst26|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated ;
+---------------------------------+--------------------+------+----------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                       ;
+---------------------------------+--------------------+------+----------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                        ;
+---------------------------------+--------------------+------+----------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------+
; Source assignments for d_latch:inst6|altsyncram0:inst28|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated ;
+---------------------------------+--------------------+------+----------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                       ;
+---------------------------------+--------------------+------+----------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                        ;
+---------------------------------+--------------------+------+----------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: d_latch:inst6|lpm_shiftreg0:inst55|lpm_shiftreg:lpm_shiftreg_component ;
+------------------------+---------+----------------------------------------------------------------------------------+
; Parameter Name         ; Value   ; Type                                                                             ;
+------------------------+---------+----------------------------------------------------------------------------------+
; LPM_WIDTH              ; 16      ; Signed Integer                                                                   ;
; LPM_DIRECTION          ; LEFT    ; Untyped                                                                          ;
; LPM_AVALUE             ; UNUSED  ; Untyped                                                                          ;
; LPM_SVALUE             ; UNUSED  ; Untyped                                                                          ;
; DEVICE_FAMILY          ; Cyclone ; Untyped                                                                          ;
; AUTO_CARRY_CHAINS      ; ON      ; AUTO_CARRY                                                                       ;
; IGNORE_CARRY_BUFFERS   ; OFF     ; IGNORE_CARRY                                                                     ;
; AUTO_CASCADE_CHAINS    ; ON      ; AUTO_CASCADE                                                                     ;
; IGNORE_CASCADE_BUFFERS ; OFF     ; IGNORE_CASCADE                                                                   ;
+------------------------+---------+----------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".