ads7844.map.rpt

本源码介绍了ADS7844 AD转换芯片的VHDL控制器。

; Ignore CASCADE Buffers                                                         ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                          ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore LCELL Buffers                                                           ; Off                ; Off                ;
; Ignore SOFT Buffers                                                            ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                                 ; Off                ; Off                ;
; Optimization Technique -- Cyclone                                              ; Balanced           ; Balanced           ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II/Cyclone III ; 70                 ; 70                 ;
; Auto Carry Chains                                                              ; On                 ; On                 ;
; Auto Open-Drain Pins                                                           ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                          ; Off                ; Off                ;
; Perform gate-level register retiming                                           ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax                         ; On                 ; On                 ;
; Auto ROM Replacement                                                           ; On                 ; On                 ;
; Auto RAM Replacement                                                           ; On                 ; On                 ;
; Auto Shift Register Replacement                                                ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                                  ; On                 ; On                 ;
; Allow Synchronous Control Signals                                              ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                         ; Off                ; Off                ;
; Auto RAM Block Balancing                                                       ; On                 ; On                 ;
; Auto RAM to Logic Cell Conversion                                              ; Off                ; Off                ;
; Auto Resource Sharing                                                          ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                             ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                             ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                                  ; Off                ; Off                ;
; Ignore translate_off and synthesis_off directives                              ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                             ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                             ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                               ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                                   ; Normal compilation ; Normal compilation ;
; HDL message level                                                              ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                                ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                       ; 100                ; 100                ;
; Clock MUX Protection                                                           ; On                 ; On                 ;
; Use smart compilation                                                          ; Off                ; Off                ;
+--------------------------------------------------------------------------------+--------------------+--------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                       ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                       ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------+
; lpm_shiftreg0.vhd                ; yes             ; User VHDL File                     ; D:/我的先进院D盘/myaltera/ads7844/lpm_shiftreg0.vhd                ;
; fq.vhd                           ; yes             ; User VHDL File                     ; D:/我的先进院D盘/myaltera/ads7844/fq.vhd                           ;
; ads7844.bdf                      ; yes             ; User Block Diagram/Schematic File  ; D:/我的先进院D盘/myaltera/ads7844/ads7844.bdf                      ;
; fq_cs.vhd                        ; yes             ; User VHDL File                     ; D:/我的先进院D盘/myaltera/ads7844/fq_cs.vhd                        ;
; addr_1.vhd                       ; yes             ; User VHDL File                     ; D:/我的先进院D盘/myaltera/ads7844/addr_1.vhd                       ;
; to_ad.bdf                        ; yes             ; User Block Diagram/Schematic File  ; D:/我的先进院D盘/myaltera/ads7844/to_ad.bdf                        ;
; dff_2.vhd                        ; yes             ; User VHDL File                     ; D:/我的先进院D盘/myaltera/ads7844/dff_2.vhd                        ;
; cs_pulse.bdf                     ; yes             ; User Block Diagram/Schematic File  ; D:/我的先进院D盘/myaltera/ads7844/cs_pulse.bdf                     ;
; cs_wide.vhd                      ; yes             ; User VHDL File                     ; D:/我的先进院D盘/myaltera/ads7844/cs_wide.vhd                      ;
; d_latch.bdf                      ; yes             ; User Block Diagram/Schematic File  ; D:/我的先进院D盘/myaltera/ads7844/d_latch.bdf                      ;
; 74165b.bdf                       ; yes             ; Megafunction                       ; c:/altera/71/quartus/libraries/others/maxplus2/74165b.bdf          ;
; lpm_shiftreg.tdf                 ; yes             ; Megafunction                       ; c:/altera/71/quartus/libraries/megafunctions/lpm_shiftreg.tdf      ;
; lpm_constant.inc                 ; yes             ; Megafunction                       ; c:/altera/71/quartus/libraries/megafunctions/lpm_constant.inc      ;
; dffeea.inc                       ; yes             ; Megafunction                       ; c:/altera/71/quartus/libraries/megafunctions/dffeea.inc            ;
; aglobal71.inc                    ; yes             ; Megafunction                       ; c:/altera/71/quartus/libraries/megafunctions/aglobal71.inc         ;
; lpm_shiftreg2.vhd                ; yes             ; Other                              ; D:/我的先进院D盘/myaltera/ads7844/lpm_shiftreg2.vhd                ;
; 74465.bdf                        ; yes             ; Megafunction                       ; c:/altera/71/quartus/libraries/others/maxplus2/74465.bdf           ;
; 74138.bdf                        ; yes             ; Megafunction                       ; c:/altera/71/quartus/libraries/others/maxplus2/74138.bdf           ;
; altsyncram0.vhd                  ; yes             ; Other                              ; D:/我的先进院D盘/myaltera/ads7844/altsyncram0.vhd                  ;
; altsyncram.tdf                   ; yes             ; Megafunction                       ; c:/altera/71/quartus/libraries/megafunctions/altsyncram.tdf        ;
; stratix_ram_block.inc            ; yes             ; Megafunction                       ; c:/altera/71/quartus/libraries/megafunctions/stratix_ram_block.inc ;
; lpm_mux.inc                      ; yes             ; Megafunction                       ; c:/altera/71/quartus/libraries/megafunctions/lpm_mux.inc           ;
; lpm_decode.inc                   ; yes             ; Megafunction                       ; c:/altera/71/quartus/libraries/megafunctions/lpm_decode.inc        ;
; a_rdenreg.inc                    ; yes             ; Megafunction                       ; c:/altera/71/quartus/libraries/megafunctions/a_rdenreg.inc         ;
; altrom.inc                       ; yes             ; Megafunction                       ; c:/altera/71/quartus/libraries/megafunctions/altrom.inc            ;
; altram.inc                       ; yes             ; Megafunction                       ; c:/altera/71/quartus/libraries/megafunctions/altram.inc            ;
; altdpram.inc                     ; yes             ; Megafunction                       ; c:/altera/71/quartus/libraries/megafunctions/altdpram.inc          ;
; altqpram.inc                     ; yes             ; Megafunction                       ; c:/altera/71/quartus/libraries/megafunctions/altqpram.inc          ;
; db/altsyncram_s7m1.tdf           ; yes             ; Auto-Generated Megafunction        ; D:/我的先进院D盘/myaltera/ads7844/db/altsyncram_s7m1.tdf           ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------+


+---------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary             ;
+---------------------------------------------+-----------+
; Resource                                    ; Usage     ;
+---------------------------------------------+-----------+
; Total logic elements                        ; 134       ;
;     -- Combinational with no register       ; 101       ;
;     -- Register only                        ; 17        ;
;     -- Combinational with a register        ; 16        ;
;                                             ;           ;
; Logic element usage by number of LUT inputs ;           ;
;     -- 4 input functions                    ; 91        ;
;     -- 3 input functions                    ; 3         ;
;     -- 2 input functions                    ; 16        ;
;     -- 1 input functions                    ; 4         ;
;     -- 0 input functions                    ; 3         ;
;                                             ;           ;
; Logic elements by mode                      ;           ;
;     -- normal mode                          ; 130       ;
;     -- arithmetic mode                      ; 4         ;
;     -- qfbk mode                            ; 0         ;
;     -- register cascade mode                ; 0         ;
;     -- synchronous clear/load mode          ; 5         ;
;     -- asynchronous clear/load mode         ; 25        ;
;                                             ;           ;
; Total registers                             ; 33        ;
; Total logic cells in carry chains           ; 5         ;
; I/O pins                                    ; 82        ;
; Total memory bits                           ; 1024      ;
; Maximum fan-out node                        ; addr_r[2] ;
; Maximum fan-out                             ; 164       ;
; Total fan-out                               ; 1573      ;
; Average fan-out                             ; 4.57      ;