ads7844.map.rpt

本源码介绍了ADS7844 AD转换芯片的VHDL控制器。

Analysis & Synthesis report for ads7844
Mon Jan 14 16:19:15 2008
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. State Machine - |ads7844|addr_1:inst1|current_state
  9. Registers Removed During Synthesis
 10. Removed Registers Triggering Further Register Optimizations
 11. General Register Statistics
 12. Source assignments for d_latch:inst6|altsyncram0:inst33|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated
 13. Source assignments for d_latch:inst6|altsyncram0:inst34|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated
 14. Source assignments for d_latch:inst6|altsyncram0:inst31|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated
 15. Source assignments for d_latch:inst6|altsyncram0:inst32|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated
 16. Source assignments for d_latch:inst6|altsyncram0:inst29|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated
 17. Source assignments for d_latch:inst6|altsyncram0:inst30|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated
 18. Source assignments for d_latch:inst6|altsyncram0:inst26|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated
 19. Source assignments for d_latch:inst6|altsyncram0:inst28|altsyncram:altsyncram_component|altsyncram_s7m1:auto_generated
 20. Parameter Settings for User Entity Instance: d_latch:inst6|lpm_shiftreg0:inst55|lpm_shiftreg:lpm_shiftreg_component
 21. Parameter Settings for User Entity Instance: d_latch:inst6|lpm_shiftreg2:inst1|lpm_shiftreg:lpm_shiftreg_component
 22. Parameter Settings for User Entity Instance: d_latch:inst6|altsyncram0:inst33|altsyncram:altsyncram_component
 23. Parameter Settings for User Entity Instance: d_latch:inst6|altsyncram0:inst34|altsyncram:altsyncram_component
 24. Parameter Settings for User Entity Instance: d_latch:inst6|lpm_shiftreg0:inst22|lpm_shiftreg:lpm_shiftreg_component
 25. Parameter Settings for User Entity Instance: d_latch:inst6|altsyncram0:inst31|altsyncram:altsyncram_component
 26. Parameter Settings for User Entity Instance: d_latch:inst6|lpm_shiftreg0:inst35|lpm_shiftreg:lpm_shiftreg_component
 27. Parameter Settings for User Entity Instance: d_latch:inst6|altsyncram0:inst32|altsyncram:altsyncram_component
 28. Parameter Settings for User Entity Instance: d_latch:inst6|lpm_shiftreg0:inst39|lpm_shiftreg:lpm_shiftreg_component
 29. Parameter Settings for User Entity Instance: d_latch:inst6|altsyncram0:inst29|altsyncram:altsyncram_component
 30. Parameter Settings for User Entity Instance: d_latch:inst6|lpm_shiftreg0:inst43|lpm_shiftreg:lpm_shiftreg_component
 31. Parameter Settings for User Entity Instance: d_latch:inst6|altsyncram0:inst30|altsyncram:altsyncram_component
 32. Parameter Settings for User Entity Instance: d_latch:inst6|lpm_shiftreg0:inst47|lpm_shiftreg:lpm_shiftreg_component
 33. Parameter Settings for User Entity Instance: d_latch:inst6|altsyncram0:inst26|altsyncram:altsyncram_component
 34. Parameter Settings for User Entity Instance: d_latch:inst6|lpm_shiftreg0:inst51|lpm_shiftreg:lpm_shiftreg_component
 35. Parameter Settings for User Entity Instance: d_latch:inst6|altsyncram0:inst28|altsyncram:altsyncram_component
 36. lpm_shiftreg Parameter Settings by Entity Instance
 37. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Mon Jan 14 16:19:15 2008    ;
; Quartus II Version          ; 7.1 Build 156 04/30/2007 SJ Full Version ;
; Revision Name               ; ads7844                                  ;
; Top-level Entity Name       ; ads7844                                  ;
; Family                      ; Cyclone                                  ;
; Total logic elements        ; 134                                      ;
; Total pins                  ; 82                                       ;
; Total virtual pins          ; 0                                        ;
; Total memory bits           ; 1,024                                    ;
; Total PLLs                  ; 0                                        ;
+-----------------------------+------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                            ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                         ; Setting            ; Default Value      ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                         ; EP1C6Q240C6        ;                    ;
; Top-level entity name                                                          ; ads7844            ; ads7844            ;
; Family name                                                                    ; Cyclone            ; Stratix            ;
; Restructure Multiplexers                                                       ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                            ; Off                ; Off                ;
; Preserve fewer node names                                                      ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                      ; Off                ; Off                ;
; Verilog Version                                                                ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                                   ; VHDL93             ; VHDL93             ;
; State Machine Processing                                                       ; Auto               ; Auto               ;
; Safe State Machine                                                             ; Off                ; Off                ;
; Extract Verilog State Machines                                                 ; On                 ; On                 ;
; Extract VHDL State Machines                                                    ; On                 ; On                 ;
; Ignore Verilog initial constructs                                              ; Off                ; Off                ;
; Add Pass-Through Logic to Inferred RAMs                                        ; On                 ; On                 ;
; NOT Gate Push-Back                                                             ; On                 ; On                 ;
; Power-Up Don't Care                                                            ; On                 ; On                 ;
; Remove Redundant Logic Cells                                                   ; Off                ; Off                ;
; Remove Duplicate Registers                                                     ; On                 ; On                 ;
; Ignore CARRY Buffers                                                           ; Off                ; Off                ;