sfifo.v

该源码是已经通过综合编译

`timescale 1ns/1ns

module sfifo(
     clk,
     rst,
     data_in,
     write,
     read,
     data_out,
     empty,
     full,
     al_full,
     half,
     al_empty
     );

// parameter definition
parameter    DATA_WIDTH    = 8;
parameter    ADDRESS_WIDTH = 6;
parameter    FIFO_DEPTH    = 64;
parameter    ALMOST_EMPTY  = 8;
parameter    ALMOST_FULL   = 56;
parameter    HALF          = 32;

input clk;
input rst;
input [DATA_WIDTH-1:0] data_in;
input read;
input write;

output [DATA_WIDTH-1:0] data_out;
output empty;
output full;
output al_full;
output half;
output al_empty;

//signal definition
//reg    [DATA_WIDTH-1:0]     data_out;
reg    [DATA_WIDTH-1:0]     mem [FIFO_DEPTH-1:0];
reg    [ADDRESS_WIDTH-1:0]  write_ptr;
reg    [ADDRESS_WIDTH-1:0]  read_ptr;
reg    [ADDRESS_WIDTH:0]    ptr_gap;
wire                        read_enable;
wire                        write_enable;

assign read_enable = read & !empty;
assign write_enable = write & !full;

// mem logic
/*always@(posedge clk or negedge rst) begin
    if(!rst) begin
        data_out <= 0;
    end
    else begin
        if(read_enable) begin
            data_out <= mem[read_ptr];
        end
        if(write_enable) begin
            mem[write_ptr] <= data_in;
        end 
    end
end */


//mem logic
always @(posedge clk) begin
    if(write_enable) begin
        mem[write_ptr] <= data_in;
    end
end

assign data_out = mem[read_ptr];

//write_ptr logic
always@(posedge clk or negedge rst) begin
    if(!rst) begin
        write_ptr <= 0;
    end
    else begin
        if(write_enable) begin
            write_ptr <= write_ptr + 1;
        end
    end
end

//read_ptr logic
always@(posedge clk or negedge rst) begin
    if(!rst) begin
        read_ptr <= 0;
    end
    else begin
        if(read_enable) begin
            read_ptr <= read_ptr + 1;
        end
    end
end    

//ptr_gap logic
always@(posedge clk or negedge rst) begin
    if(!rst) begin
        ptr_gap <= 0;
    end
    else begin
        if(!read_enable & write_enable) begin
            ptr_gap <= ptr_gap + 1;
        end
        else if (!write_enable & read_enable) begin
            ptr_gap <= ptr_gap - 1;
        end
    end
end

            
assign al_full = (ptr_gap == ALMOST_FULL);
assign al_empty = (ptr_gap == ALMOST_EMPTY);
assign half = (ptr_gap == HALF);
assign full = (ptr_gap == FIFO_DEPTH);
assign empty = (ptr_gap == 0);

endmodule