test_sfifo.v

该源码是已经通过综合编译

`timescale 1ns/1ns

module test_sfifo;
       
parameter    DATA_WIDTH    = 8;
parameter    ADDRESS_WIDTH = 6;
parameter    FIFO_DEPTH    = 64;
    
reg   clk;
reg   rst;
reg   read;
reg   write;
reg   [DATA_WIDTH-1:0] data_in;
wire  [DATA_WIDTH-1:0] data_out;
wire  al_full;
wire  al_empty;
wire  half;
wire  full;
wire  empty;
       
initial #10000 $stop;

initial begin 
   rst =0; 
   #50 rst = 1;
end

initial begin
  clk = 0;
  forever #10 clk = ~clk;
end 

initial begin     
          read =0 ;
          write =0;
          data_in = 0;
end

initial begin
    repeat (50)    #40 read = ~read;
    #40 repeat (300) #30 read = ~read;
    #50 read = 1;
end

initial begin
    #50 write = 1;
    #4000 write =0;
    repeat (100)    #40 write = ~write;
end
   
always @ (posedge clk or negedge rst)begin
   if (!rst) begin
       data_in <= 0;
   end
   else  if(write & !full) begin
       data_in <= data_in + 1;
   end
end //always @ (posedge clk_write or negedge rst)

sfifo sfifo(
     clk,
     rst,
     data_in,
     write,
     read,
     data_out,
     empty,
     full,
     al_full,
     half,
     al_empty
     );

//initial
//$monitor ($time, "     rst=%b,data_in=%b,data_out=%b,write_enable=%b,read_enable=%b,full=%b,empty=%b,write=%b,read=%b",
//            rst,data_in,data_out,write_enable,read_enable,full,empty,write,read);

endmodule