tap.v

来自「verilog 实现的 jtag TAP」· Verilog 代码 · 共 587 行 · 第 1/2 页

/**********************************************************************************
*                                                                                 *
*   This verilog file is a part of the Boundary Scan Implementation and comes in  *
*   a pack with several other files. It is fully IEEE 1149.1 compliant.           *
*   For details check www.opencores.org (pdf files, bsdl file, etc.)              *
*                                                                                 *
*  Copyright (C) 2000 Igor Mohor ([e-mail]) and OPENCORES.ORG          *
*                                                                                 *
*  This program is free software; you can redistribute it and/or modify           *
*  it under the terms of the GNU General Public License as published by           *
*  the Free Software Foundation; either version 2 of the License, or              *
*  (at your option) any later version.                                            *
*                                                                                 *
*  See the file COPYING for the full details of the license.                      *
*                                                                                 *
*  OPENCORES.ORG is looking for new open source IP cores and developers that      *
*  would like to help in our mission.                                             *
*                                                                                 *
**********************************************************************************/


// Top module
module TAP(P_TMS, P_TCK, P_TRST, P_TDI, P_TDO, 
		TestSignal,
		InputPin,
		Output3Pin,
		Output2Pin,
		BidirectionalPin
		);

`define BSLength 14

supply1 vcc;
supply0 gnd;

// Instructions specified by the IEEE-1149.1
parameter EXTEST          = 4'b0000;
parameter SAMPLE_PRELOAD  = 4'b0001;
parameter IDCODE          = 4'b0010;
parameter BYPASS          = 4'b1111;


input P_TMS, P_TCK;
input P_TRST, P_TDI;

output P_TDO;

input [1:0] InputPin;						// Input pin
output [1:0] Output3Pin;  			// Output pin with tristate control
output [1:0] Output2Pin;  			// Output pin without tristate control
inout [1:0] BidirectionalPin;		// Input/Output pin (with tristate control)

output [5:0]TestSignal; 				// Signals for testing purposes (can be deleted)

wire TCK = P_TCK;
wire TCKn = ~P_TCK;
wire TMS = P_TMS;
wire TDI = P_TDI;

wire TRST = P_TRST;							// TRST is active high (for easier development). Should be change to active low
//wire TRST = ~P_TRST;					// active low

reg TestLogicReset;
reg RunTestIdle;
reg SelectDRScan;
reg CaptureDR;
reg ShiftDR;
reg Exit1DR;
reg PauseDR;
reg Exit2DR;
reg UpdateDR;

reg SelectIRScan;
reg CaptureIR;
reg ShiftIR;
reg Exit1IR;
reg PauseIR;
reg Exit2IR;
reg UpdateIR;



/**********************************************************************************
*																																									*
*		TAP State Machine: Fully JTAG compliant																				*
*																																									*
*		P_TRST must toggle at the beginning if PowerONReset signal is not present			*
*		in the design.																																*
*																																									*
*																																									*
*																																									*
**********************************************************************************/
//wire RESET = TRST | PowerONReset;							// If PowerONReset signal is used in the design
wire RESET = TRST;															// If no PowerONReset signal is used in the design

// TestLogicReset state
always @ (posedge TCK or posedge RESET)
begin
	if(RESET)
		TestLogicReset<=1;
	else
		begin
			if(TMS & (TestLogicReset | SelectIRScan))
				TestLogicReset<=1;
			else
				TestLogicReset<=0;
		end
end

// RunTestIdle state
always @ (posedge TCK or posedge RESET)
begin
	if(RESET)
		RunTestIdle<=0;
	else
		begin
			if(~TMS & (TestLogicReset | RunTestIdle | UpdateDR | UpdateIR))
				RunTestIdle<=1;
			else
				RunTestIdle<=0;
		end
end

// SelectDRScan state
always @ (posedge TCK or posedge RESET)
begin
	if(RESET)
		SelectDRScan<=0;
	else
		begin
			if(TMS & (RunTestIdle | UpdateDR | UpdateIR))
				SelectDRScan<=1;
			else
				SelectDRScan<=0;
		end
end

// CaptureDR state
always @ (posedge TCK or posedge RESET)
begin
	if(RESET)
		CaptureDR<=0;
	else
		begin
			if(~TMS & SelectDRScan)
				CaptureDR<=1;
			else
				CaptureDR<=0;
		end
end

// ShiftDR state
always @ (posedge TCK or posedge RESET)
begin
	if(RESET)
		ShiftDR<=0;
	else
		begin
			if(~TMS & (CaptureDR | ShiftDR | Exit2DR))
				ShiftDR<=1;
			else
				ShiftDR<=0;
		end
end

// Exit1DR state
always @ (posedge TCK or posedge RESET)
begin
	if(RESET)
		Exit1DR<=0;
	else
		begin
			if(TMS & (CaptureDR | ShiftDR))
				Exit1DR<=1;
			else
				Exit1DR<=0;
		end
end

// PauseDR state
always @ (posedge TCK or posedge RESET)
begin
	if(RESET)
		PauseDR<=0;
	else
		begin
			if(~TMS & (Exit1DR | PauseDR))
				PauseDR<=1;
			else
				PauseDR<=0;
		end
end

// Exit2DR state
always @ (posedge TCK or posedge RESET)
begin
	if(RESET)
		Exit2DR<=0;
	else
		begin
			if(TMS & PauseDR)
				Exit2DR<=1;
			else
				Exit2DR<=0;
		end
end

// UpdateDR state
always @ (posedge TCK or posedge RESET)
begin
	if(RESET)
		UpdateDR<=0;
	else
		begin
			if(TMS & (Exit1DR | Exit2DR))
				UpdateDR<=1;
			else
				UpdateDR<=0;
		end
end

// SelectIRScan state
always @ (posedge TCK or posedge RESET)
begin
	if(RESET)
		SelectIRScan<=0;
	else
		begin
			if(TMS & SelectDRScan)
				SelectIRScan<=1;
			else
				SelectIRScan<=0;
		end
end

// CaptureIR state
always @ (posedge TCK or posedge RESET)
begin
	if(RESET)
		CaptureIR<=0;
	else
		begin
			if(~TMS & SelectIRScan)
				CaptureIR<=1;
			else
				CaptureIR<=0;
		end
end

// ShiftIR state
always @ (posedge TCK or posedge RESET)
begin
	if(RESET)
		ShiftIR<=0;
	else
		begin
			if(~TMS & (CaptureIR | ShiftIR | Exit2IR))
				ShiftIR<=1;
			else
				ShiftIR<=0;
		end
end

// Exit1IR state
always @ (posedge TCK or posedge RESET)
begin
	if(RESET)
		Exit1IR<=0;
	else
		begin
			if(TMS & (CaptureIR | ShiftIR))
				Exit1IR<=1;
			else
				Exit1IR<=0;
		end
end

// PauseIR state
always @ (posedge TCK or posedge RESET)
begin
	if(RESET)
		PauseIR<=0;
	else
		begin
			if(~TMS & (Exit1IR | PauseIR))
				PauseIR<=1;
			else
				PauseIR<=0;
		end
end

// Exit2IR state
always @ (posedge TCK or posedge RESET)
begin