tap.v

来自「verilog 实现的 jtag TAP」· Verilog 代码 · 共 587 行 · 第 1/2 页

	if(RESET)
		Exit2IR<=0;
	else
		begin
			if(TMS & PauseIR)
				Exit2IR<=1;
			else
				Exit2IR<=0;
		end
end

// UpdateIR state
always @ (posedge TCK or posedge RESET)
begin
	if(RESET)
		UpdateIR<=0;
	else
		begin
			if(TMS & (Exit1IR | Exit2IR))
				UpdateIR<=1;
			else
				UpdateIR<=0;
		end
end

/**********************************************************************************
*																																									*
*		End: TAP State Machine																												*
*																																									*
**********************************************************************************/



/**********************************************************************************
*																																									*
*		JTAG_SIR:	JTAG Shift Instruction Register: Instruction shifted in, status out	*
*		JTAG_IR:	JTAG Instruction Register: Updated on UpdateIR or TestLogicReset		*
*																																									*
*		Status is shifted out.																												*
*																																									*
**********************************************************************************/
wire [1:0]Status = 2'b10;		// Holds current chip status. Core should return this status. For now a constant is used.

reg [3:0]JTAG_SIR;	// Register used for shifting in and out
reg [3:0]JTAG_IR;		// Instruction register
reg TDOInstruction;

always @ (posedge TCK)
begin
	if(CaptureIR)
		begin
			JTAG_SIR[1:0] <= 2'b01;				// This value is fixed for easier fault detection
			JTAG_SIR[3:2] <= Status[1:0];	// Current status of chip
		end
	else
		begin
			if(ShiftIR)
				begin
					JTAG_SIR[3:0] <= JTAG_SIR[3:0] >> 1;
					JTAG_SIR[3] <= TDI;
				end
		end
end

// Updating JTAG_IR (Instruction Register)
always @ (posedge TCK or posedge TestLogicReset)
begin
	if(TestLogicReset)
		JTAG_IR <= IDCODE;
	else
		begin
			if(UpdateIR)
				JTAG_IR <= JTAG_SIR;
		end
end

//TDO is changing on the falling edge of TCK
always @ (negedge TCK)
begin
	if(ShiftIR)
		TDOInstruction <= JTAG_SIR[0];
end
	
/**********************************************************************************
*																																									*
*		End: JTAG_SIR																																	*
*		End: JTAG_IR																																	*
*																																									*
**********************************************************************************/


/**********************************************************************************
*																																									*
*		JTAG_SDR:	JTAG Shift Data Register: Data shifted in and out										*
*		JTAG_DR:	JTAG Data Register: Updated on UpdateDR															*
*																																									*
*		Data that is shifted out can be a chip ID or a requested data (register value,*
*		memory value, etc.																														*
*																																									*
**********************************************************************************/
wire [32:0] IDCodeValue = 33'b011000011110000111100001111000011; // ID value (constant 0x0c3c3c3c3). IDCODE is 32-bit long, so the MSB is not used
wire [32:0] DataValue   = 33'b101001100011100001111000111001101; // This should be data from the core. For now a constant value 0x14c70f1cd is used
wire [32:0] RequestedData = (JTAG_IR==IDCODE)? IDCodeValue : DataValue;	// This is to be expanded with number of user registers

reg [32:0]JTAG_SDR;	// Register used for shifting in and out
reg [32:0]JTAG_DR;		// Data register
reg TDOData;

always @ (posedge TCK)
begin
	if(CaptureDR)
		JTAG_SDR <= RequestedData;			// DataResponse contains data requested in previous cycle
	else
		begin
			if(ShiftDR)
				begin
					JTAG_SDR <= JTAG_SDR >> 1;
					JTAG_SDR[32] <= TDI;
				end
		end
end

// Updating JTAG_DR (Data Register)
always @ (posedge TCK)
begin
	if(UpdateDR)
		JTAG_DR <= JTAG_SDR;
end

//TDO is changing on the falling edge of TCK
always @ (negedge TCK)
begin
	if(ShiftDR)
		TDOData <= JTAG_SDR[0];
end

/**********************************************************************************
*																																									*
*		End: JTAG_SDR																																	*
*		End: JTAG_DR																																	*
*																																									*
**********************************************************************************/



/**********************************************************************************
*																																									*
*		Bypass logic																																	*
*																																									*
**********************************************************************************/
reg BypassRegister;
reg TDOBypassed;

always @ (posedge TCK)
begin
	if(ShiftDR)
		BypassRegister<=TDI;
end

always @ (negedge TCK)
begin
		TDOBypassed<=BypassRegister;
end
/**********************************************************************************
*																																									*
*		End: Bypass logic																															*
*																																									*
**********************************************************************************/



/**********************************************************************************
*																																									*
*		Boundary Scan Logic																														*
*																																									*
**********************************************************************************/
wire [`BSLength-1:0]ExitFromBSCell;


wire [3:0]ToOutputEnable;
wire [1:0]BidirectionalBuffered;

wire [5:0]FromCore = 6'h0;   			// This are signals that core send to output (or bidirectional) pins. We have no core, so they are all zero.
wire [3:0]ControlPIN = 4'h0;			// Core control signals. Since no core is used, they are fixed to zero.

// buffers
assign BidirectionalBuffered[1:0] = BidirectionalPin[1:0];								// Inputs of bidirectional signals should be buffered (as seen below)
//IBUF buffer0 (.I(BidirectionalPin[0]), .O(BidirectionalBuffered[0]));
//IBUF buffer1 (.I(BidirectionalPin[1]), .O(BidirectionalBuffered[1]));

//wire ExtTestEnabled = (JTAG_IR==EXTEST) | (JTAG_IR==SAMPLE_PRELOAD);
wire ExtTestEnabled = (JTAG_IR==EXTEST);


// BOUNDARY SCAN REGISTER
// closest to TDO
InputCell BS0     ( .InputPin(InputPin[0]),              .FromPreviousBSCell(ExitFromBSCell[12]), .CaptureDR(CaptureDR), .ShiftDR(ShiftDR), .TCK(TCK), .ToNextBSCell(ExitFromBSCell[`BSLength-1]));
InputCell BS1     ( .InputPin(InputPin[1]),              .FromPreviousBSCell(ExitFromBSCell[11]), .CaptureDR(CaptureDR), .ShiftDR(ShiftDR), .TCK(TCK), .ToNextBSCell(ExitFromBSCell[12]));

OutputCell BS2    ( .FromCore(FromCore[0]),              .FromPreviousBSCell(ExitFromBSCell[10]), .CaptureDR(CaptureDR), .ShiftDR(ShiftDR), .TCK(TCK), .ToNextBSCell(ExitFromBSCell[11]), .UpdateDR(UpdateDR), .extest(ExtTestEnabled), .FromOutputEnable(ToOutputEnable[0]), .TristatedPin(Output3Pin[0]));
ControlCell BS3   ( .OutputControl(ControlPIN[0]),       .FromPreviousBSCell(ExitFromBSCell[9]),  .CaptureDR(CaptureDR), .ShiftDR(ShiftDR), .TCK(TCK), .ToNextBSCell(ExitFromBSCell[10]), .UpdateDR(UpdateDR), .extest(ExtTestEnabled), .ToOutputEnable(ToOutputEnable[0]));
                                                                                                                                                                                          
OutputCell BS4    ( .FromCore(FromCore[1]),              .FromPreviousBSCell(ExitFromBSCell[8]),  .CaptureDR(CaptureDR), .ShiftDR(ShiftDR), .TCK(TCK), .ToNextBSCell(ExitFromBSCell[9]),  .UpdateDR(UpdateDR), .extest(ExtTestEnabled), .FromOutputEnable(ToOutputEnable[1]), .TristatedPin(Output3Pin[1]));
ControlCell BS5   ( .OutputControl(ControlPIN[1]),       .FromPreviousBSCell(ExitFromBSCell[7]),  .CaptureDR(CaptureDR), .ShiftDR(ShiftDR), .TCK(TCK), .ToNextBSCell(ExitFromBSCell[8]),  .UpdateDR(UpdateDR), .extest(ExtTestEnabled), .ToOutputEnable(ToOutputEnable[1]));
                                                                                                                                                                                          
InputCell BS6     ( .InputPin(BidirectionalBuffered[0]), .FromPreviousBSCell(ExitFromBSCell[6]),  .CaptureDR(CaptureDR), .ShiftDR(ShiftDR), .TCK(TCK), .ToNextBSCell(ExitFromBSCell[7]));
OutputCell BS7    ( .FromCore(FromCore[2]),              .FromPreviousBSCell(ExitFromBSCell[5]),  .CaptureDR(CaptureDR), .ShiftDR(ShiftDR), .TCK(TCK), .ToNextBSCell(ExitFromBSCell[6]),  .UpdateDR(UpdateDR), .extest(ExtTestEnabled), .FromOutputEnable(ToOutputEnable[2]), .TristatedPin(BidirectionalPin[0]));
ControlCell BS8   ( .OutputControl(ControlPIN[2]),       .FromPreviousBSCell(ExitFromBSCell[4]),  .CaptureDR(CaptureDR), .ShiftDR(ShiftDR), .TCK(TCK), .ToNextBSCell(ExitFromBSCell[5]),  .UpdateDR(UpdateDR), .extest(ExtTestEnabled), .ToOutputEnable(ToOutputEnable[2]));
                                                                                                                                                                                          
InputCell BS9     ( .InputPin(BidirectionalBuffered[1]), .FromPreviousBSCell(ExitFromBSCell[3]),  .CaptureDR(CaptureDR), .ShiftDR(ShiftDR), .TCK(TCK), .ToNextBSCell(ExitFromBSCell[4]));
OutputCell BS10   ( .FromCore(FromCore[3]),              .FromPreviousBSCell(ExitFromBSCell[2]),  .CaptureDR(CaptureDR), .ShiftDR(ShiftDR), .TCK(TCK), .ToNextBSCell(ExitFromBSCell[3]),  .UpdateDR(UpdateDR), .extest(ExtTestEnabled), .FromOutputEnable(ToOutputEnable[3]), .TristatedPin(BidirectionalPin[1]));
ControlCell BS11  ( .OutputControl(ControlPIN[3]),       .FromPreviousBSCell(ExitFromBSCell[1]),  .CaptureDR(CaptureDR), .ShiftDR(ShiftDR), .TCK(TCK), .ToNextBSCell(ExitFromBSCell[2]),  .UpdateDR(UpdateDR), .extest(ExtTestEnabled), .ToOutputEnable(ToOutputEnable[3]));
                                                                                                                                                                                          
OutputCell BS12   ( .FromCore(FromCore[4]),              .FromPreviousBSCell(ExitFromBSCell[0]),  .CaptureDR(CaptureDR), .ShiftDR(ShiftDR), .TCK(TCK), .ToNextBSCell(ExitFromBSCell[1]),  .UpdateDR(UpdateDR), .extest(ExtTestEnabled), .FromOutputEnable(vcc),               .TristatedPin(Output2Pin[0]));
OutputCell BS13   ( .FromCore(FromCore[5]),              .FromPreviousBSCell(TDI),                .CaptureDR(CaptureDR), .ShiftDR(ShiftDR), .TCK(TCK), .ToNextBSCell(ExitFromBSCell[0]),  .UpdateDR(UpdateDR), .extest(ExtTestEnabled), .FromOutputEnable(vcc),               .TristatedPin(Output2Pin[1]));
// closest to TDI


/**********************************************************************************
*																																									*
*		End: Boundary Scan Logic																											*
*																																									*
**********************************************************************************/





/**********************************************************************************
*																																									*
*		Multiplexing TDO and Tristate control																					*
*																																									*
**********************************************************************************/
wire TDOShifted;
assign TDOShifted = (ShiftIR | Exit1IR)? TDOInstruction : TDOData;

reg TDOMuxed;


// This multiplexing can be expanded with number of user registers
always @ (JTAG_IR or TDOShifted or ExitFromBSCell or TDOBypassed)
begin
	case(JTAG_IR)
		IDCODE: // Reading ID code
			begin
				TDOMuxed<=TDOShifted;
			end
		SAMPLE_PRELOAD:	// Sampling/Preloading
			begin
				TDOMuxed<=ExitFromBSCell[`BSLength-1];
			end
		EXTEST:	// External test
			begin
				TDOMuxed<=ExitFromBSCell[`BSLength-1];
			end
		default:	// BYPASS instruction
			begin
				TDOMuxed<=TDOBypassed;
			end
	endcase
end



// Tristate control for P_TDO pin
assign P_TDO = (ShiftIR | ShiftDR | Exit1IR | Exit1DR)? TDOMuxed : 1'bz;


/**********************************************************************************
*																																									*
*		End:	Multiplexing TDO and Tristate control																		*
*																																									*
**********************************************************************************/






// Test Signals (can be deleted)

assign TestSignal[0] = CaptureDR;
assign TestSignal[1] = RunTestIdle;
assign TestSignal[2] = ShiftDR;
assign TestSignal[3] = UpdateDR;

assign TestSignal[4] = JTAG_IR[0];
assign TestSignal[5] = JTAG_IR[1];



endmodule	// TAP