pn_catch.v

采用匹配滤波

	input [1022:0]reg_pn;
	output catch;

	reg [9:0]count_i,count_q;	//IQ路按chip累加结果（相关后1的个数）
	//I路按chip累加中间结果
	reg [5:0]count_i_0,count_i_1,count_i_2,count_i_3,count_i_4,count_i_5,count_i_6,count_i_7,count_i_8,count_i_9,count_i_10,count_i_11,count_i_12,count_i_13,count_i_14,count_i_15,count_i_16,count_i_17,count_i_18,count_i_19,count_i_20,count_i_21,count_i_22,count_i_23,count_i_24,count_i_25,count_i_26,count_i_27,count_i_28,count_i_29,count_i_30,count_i_31;
	//Q路按chip累加中间结果
	reg [5:0]count_q_0,count_q_1,count_q_2,count_q_3,count_q_4,count_q_5,count_q_6,count_q_7,count_q_8,count_q_9,count_q_10,count_q_11,count_q_12,count_q_13,count_q_14,count_q_15,count_q_16,count_q_17,count_q_18,count_q_19,count_q_20,count_q_21,count_q_22,count_q_23,count_q_24,count_q_25,count_q_26,count_q_27,count_q_28,count_q_29,count_q_30,count_q_31;
	reg [8:0]mod_i ,mod_q;	 	//IQ两路相关累加的幅值
	reg [4:0]MOD;				 	//IQ平方和开方幅值
	reg [10:0]count_reg,A,B;		 	//存储器计数器,下存储门限，上存储门限
	reg [7:0]big_reg[63:0];	//每一个chip的相关累加和的累加存储器
	reg catch,catch1;						//捕获脉冲,第一阶段粗捕获标志
	reg enable;						//工作使能信号(存储器计数器达到2045后模块开始工作)
	reg [5:0] C;					//参考计数器

			//////////////////////
			//IQ路按chip累加结果//
			//////////////////////
	always @(posedge clk or posedge reset)
		begin
			if (reset)
				begin
					count_i    <= 10'b0;	 count_q    <= 10'b0;