_primary.vhd

来自「采用匹配滤波」· VHDL 代码 · 共 10 行

library verilog;
use verilog.vl_types.all;
entity p2 is
    generic(
        PERIOD          : integer := 9092;
        DUTY_CYCLE      : real    := 0.500000;
        OFFSET          : integer := 0
    );
end p2;