_primary.vhd

来自「采用匹配滤波」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity loop_decode_code is
    port(
        wr_count_fifo   : in     vl_logic_vector(1 downto 0);
        add_31bit       : in     vl_logic_vector(30 downto 0);
        reset           : in     vl_logic;
        clk110          : in     vl_logic;
        fifo_read_clk   : out    vl_logic
    );
end loop_decode_code;