pngenchuan_18.tan.rpt

生成18级的m序列的VerilogHDL程序

; N/A   ; None         ; 3.456 ns   ; OUTEN ; REGISTER[1]  ; CLK      ;
; N/A   ; None         ; 3.456 ns   ; OUTEN ; REGISTER[11] ; CLK      ;
; N/A   ; None         ; 3.456 ns   ; OUTEN ; REGISTER[10] ; CLK      ;
; N/A   ; None         ; 3.456 ns   ; OUTEN ; REGISTER[9]  ; CLK      ;
; N/A   ; None         ; 3.456 ns   ; OUTEN ; REGISTER[8]  ; CLK      ;
; N/A   ; None         ; 3.456 ns   ; OUTEN ; REGISTER[7]  ; CLK      ;
; N/A   ; None         ; 3.446 ns   ; OUTEN ; REGISTER[14] ; CLK      ;
; N/A   ; None         ; 3.446 ns   ; OUTEN ; REGISTER[13] ; CLK      ;
; N/A   ; None         ; 3.446 ns   ; OUTEN ; REGISTER[12] ; CLK      ;
; N/A   ; None         ; 3.357 ns   ; OUTEN ; PNOUT~reg0   ; CLK      ;
; N/A   ; None         ; 1.898 ns   ; RST   ; PNOUT~reg0   ; CLK      ;
+-------+--------------+------------+-------+--------------+----------+


+---------------------------------------------------------------------+
; tco                                                                 ;
+-------+--------------+------------+------------+-------+------------+
; Slack ; Required tco ; Actual tco ; From       ; To    ; From Clock ;
+-------+--------------+------------+------------+-------+------------+
; N/A   ; None         ; 6.429 ns   ; PNOUT~reg0 ; PNOUT ; CLK        ;
+-------+--------------+------------+------------+-------+------------+


+---------------------------------------------------------------------------+
; th                                                                        ;
+---------------+-------------+-----------+-------+--------------+----------+
; Minimum Slack ; Required th ; Actual th ; From  ; To           ; To Clock ;
+---------------+-------------+-----------+-------+--------------+----------+
; N/A           ; None        ; -1.668 ns ; RST   ; PNOUT~reg0   ; CLK      ;
; N/A           ; None        ; -3.127 ns ; OUTEN ; PNOUT~reg0   ; CLK      ;
; N/A           ; None        ; -3.216 ns ; OUTEN ; REGISTER[14] ; CLK      ;
; N/A           ; None        ; -3.216 ns ; OUTEN ; REGISTER[13] ; CLK      ;
; N/A           ; None        ; -3.216 ns ; OUTEN ; REGISTER[12] ; CLK      ;
; N/A           ; None        ; -3.226 ns ; OUTEN ; REGISTER[0]  ; CLK      ;
; N/A           ; None        ; -3.226 ns ; OUTEN ; REGISTER[17] ; CLK      ;
; N/A           ; None        ; -3.226 ns ; OUTEN ; REGISTER[6]  ; CLK      ;
; N/A           ; None        ; -3.226 ns ; OUTEN ; REGISTER[16] ; CLK      ;
; N/A           ; None        ; -3.226 ns ; OUTEN ; REGISTER[5]  ; CLK      ;
; N/A           ; None        ; -3.226 ns ; OUTEN ; REGISTER[15] ; CLK      ;
; N/A           ; None        ; -3.226 ns ; OUTEN ; REGISTER[4]  ; CLK      ;
; N/A           ; None        ; -3.226 ns ; OUTEN ; REGISTER[3]  ; CLK      ;
; N/A           ; None        ; -3.226 ns ; OUTEN ; REGISTER[2]  ; CLK      ;
; N/A           ; None        ; -3.226 ns ; OUTEN ; REGISTER[1]  ; CLK      ;
; N/A           ; None        ; -3.226 ns ; OUTEN ; REGISTER[11] ; CLK      ;
; N/A           ; None        ; -3.226 ns ; OUTEN ; REGISTER[10] ; CLK      ;
; N/A           ; None        ; -3.226 ns ; OUTEN ; REGISTER[9]  ; CLK      ;
; N/A           ; None        ; -3.226 ns ; OUTEN ; REGISTER[8]  ; CLK      ;
; N/A           ; None        ; -3.226 ns ; OUTEN ; REGISTER[7]  ; CLK      ;
+---------------+-------------+-----------+-------+--------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Wed Jan 23 15:55:12 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off PNGENchuan_18 -c PNGENchuan_18 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" Internal fmax is restricted to 420.17 MHz between source register "REGISTER[0]" and destination register "PNOUT~reg0"
    Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.726 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X75_Y1_N21; Fanout = 2; REG Node = 'REGISTER[0]'
            Info: 2: + IC(0.492 ns) + CELL(0.150 ns) = 0.642 ns; Loc. = LCCOMB_X75_Y1_N16; Fanout = 1; COMB Node = 'PNOUT~63'
            Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.726 ns; Loc. = LCFF_X75_Y1_N17; Fanout = 2; REG Node = 'PNOUT~reg0'
            Info: Total cell delay = 0.234 ns ( 32.23 % )
            Info: Total interconnect delay = 0.492 ns ( 67.77 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "CLK" to destination register is 2.777 ns
                Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'CLK'
                Info: 2: + IC(0.117 ns) + CELL(0.000 ns) = 1.096 ns; Loc. = CLKCTRL_G3; Fanout = 19; COMB Node = 'CLK~clkctrl'
                Info: 3: + IC(1.144 ns) + CELL(0.537 ns) = 2.777 ns; Loc. = LCFF_X75_Y1_N17; Fanout = 2; REG Node = 'PNOUT~reg0'
                Info: Total cell delay = 1.516 ns ( 54.59 % )
                Info: Total interconnect delay = 1.261 ns ( 45.41 % )
            Info: - Longest clock path from clock "CLK" to source register is 2.777 ns
                Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'CLK'
                Info: 2: + IC(0.117 ns) + CELL(0.000 ns) = 1.096 ns; Loc. = CLKCTRL_G3; Fanout = 19; COMB Node = 'CLK~clkctrl'
                Info: 3: + IC(1.144 ns) + CELL(0.537 ns) = 2.777 ns; Loc. = LCFF_X75_Y1_N21; Fanout = 2; REG Node = 'REGISTER[0]'
                Info: Total cell delay = 1.516 ns ( 54.59 % )
                Info: Total interconnect delay = 1.261 ns ( 45.41 % )
        Info: + Micro clock to output delay of source is 0.250 ns
        Info: + Micro setup delay of destination is -0.036 ns
Info: tsu for register "REGISTER[0]" (data pin = "OUTEN", clock pin = "CLK") is 3.456 ns
    Info: + Longest pin to register delay is 6.269 ns
        Info: 1: + IC(0.000 ns) + CELL(0.820 ns) = 0.820 ns; Loc. = PIN_Y17; Fanout = 19; PIN Node = 'OUTEN'
        Info: 2: + IC(4.789 ns) + CELL(0.660 ns) = 6.269 ns; Loc. = LCFF_X75_Y1_N21; Fanout = 2; REG Node = 'REGISTER[0]'
        Info: Total cell delay = 1.480 ns ( 23.61 % )
        Info: Total interconnect delay = 4.789 ns ( 76.39 % )
    Info: + Micro setup delay of destination is -0.036 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 2.777 ns
        Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'CLK'
        Info: 2: + IC(0.117 ns) + CELL(0.000 ns) = 1.096 ns; Loc. = CLKCTRL_G3; Fanout = 19; COMB Node = 'CLK~clkctrl'
        Info: 3: + IC(1.144 ns) + CELL(0.537 ns) = 2.777 ns; Loc. = LCFF_X75_Y1_N21; Fanout = 2; REG Node = 'REGISTER[0]'
        Info: Total cell delay = 1.516 ns ( 54.59 % )
        Info: Total interconnect delay = 1.261 ns ( 45.41 % )
Info: tco from clock "CLK" to destination pin "PNOUT" through register "PNOUT~reg0" is 6.429 ns
    Info: + Longest clock path from clock "CLK" to source register is 2.777 ns
        Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'CLK'
        Info: 2: + IC(0.117 ns) + CELL(0.000 ns) = 1.096 ns; Loc. = CLKCTRL_G3; Fanout = 19; COMB Node = 'CLK~clkctrl'
        Info: 3: + IC(1.144 ns) + CELL(0.537 ns) = 2.777 ns; Loc. = LCFF_X75_Y1_N17; Fanout = 2; REG Node = 'PNOUT~reg0'
        Info: Total cell delay = 1.516 ns ( 54.59 % )
        Info: Total interconnect delay = 1.261 ns ( 45.41 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 3.402 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X75_Y1_N17; Fanout = 2; REG Node = 'PNOUT~reg0'
        Info: 2: + IC(0.624 ns) + CELL(2.778 ns) = 3.402 ns; Loc. = PIN_V15; Fanout = 0; PIN Node = 'PNOUT'
        Info: Total cell delay = 2.778 ns ( 81.66 % )
        Info: Total interconnect delay = 0.624 ns ( 18.34 % )
Info: th for register "PNOUT~reg0" (data pin = "RST", clock pin = "CLK") is -1.668 ns
    Info: + Longest clock path from clock "CLK" to destination register is 2.777 ns
        Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'CLK'
        Info: 2: + IC(0.117 ns) + CELL(0.000 ns) = 1.096 ns; Loc. = CLKCTRL_G3; Fanout = 19; COMB Node = 'CLK~clkctrl'
        Info: 3: + IC(1.144 ns) + CELL(0.537 ns) = 2.777 ns; Loc. = LCFF_X75_Y1_N17; Fanout = 2; REG Node = 'PNOUT~reg0'
        Info: Total cell delay = 1.516 ns ( 54.59 % )
        Info: Total interconnect delay = 1.261 ns ( 45.41 % )
    Info: + Micro hold delay of destination is 0.266 ns
    Info: - Shortest pin to register delay is 4.711 ns
        Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_M2; Fanout = 2; PIN Node = 'RST'
        Info: 2: + IC(3.229 ns) + CELL(0.419 ns) = 4.627 ns; Loc. = LCCOMB_X75_Y1_N16; Fanout = 1; COMB Node = 'PNOUT~63'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 4.711 ns; Loc. = LCFF_X75_Y1_N17; Fanout = 2; REG Node = 'PNOUT~reg0'
        Info: Total cell delay = 1.482 ns ( 31.46 % )
        Info: Total interconnect delay = 3.229 ns ( 68.54 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 119 megabytes of memory during processing
    Info: Processing ended: Wed Jan 23 15:55:13 2008
    Info: Elapsed time: 00:00:01