pngenchuan_18.v

来自「生成18级的m序列的VerilogHDL程序」· Verilog 代码 · 共 34 行

//*********************************************
//file:     PNGENchuan_18.v
//desp:     PN m sequence genenrator
//autor:    sunhao
//data:     9th.jan.2008
//version:  0.1
//modified:
//*********************************************//
module PNGENchuan_18(
RST,//high level rest 
CLK,//clock output enable
PNOUT,//PN data output
OUTEN // PN output enable
);

input RST,CLK,OUTEN;
output PNOUT;
reg PNOUT;
reg [17:0] REGISTER; //18	-level register

always @(posedge CLK or posedge RST)
begin
	if(RST)
		REGISTER <= 18'b111111111111111111;//input data intital
	else if(OUTEN)
		begin
		REGISTER[17:1] <= REGISTER[16:0];
		REGISTER[0] <= REGISTER[17] ^ REGISTER[6];
		   PNOUT <= REGISTER[0];
      end//if (OUTEN)
	end
endmodule