pngenchuan_18.tan.qmsg

生成18级的m序列的VerilogHDL程序

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLK register register REGISTER\[0\] PNOUT~reg0 420.17 MHz Internal " "Info: Clock \"CLK\" Internal fmax is restricted to 420.17 MHz between source register \"REGISTER\[0\]\" and destination register \"PNOUT~reg0\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.38 ns " "Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.726 ns + Longest register register " "Info: + Longest register to register delay is 0.726 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns REGISTER\[0\] 1 REG LCFF_X75_Y1_N21 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X75_Y1_N21; Fanout = 2; REG Node = 'REGISTER\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { REGISTER[0] } "NODE_NAME" } } { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.492 ns) + CELL(0.150 ns) 0.642 ns PNOUT~63 2 COMB LCCOMB_X75_Y1_N16 1 " "Info: 2: + IC(0.492 ns) + CELL(0.150 ns) = 0.642 ns; Loc. = LCCOMB_X75_Y1_N16; Fanout = 1; COMB Node = 'PNOUT~63'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.642 ns" { REGISTER[0] PNOUT~63 } "NODE_NAME" } } { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 0.726 ns PNOUT~reg0 3 REG LCFF_X75_Y1_N17 2 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.726 ns; Loc. = LCFF_X75_Y1_N17; Fanout = 2; REG Node = 'PNOUT~reg0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { PNOUT~63 PNOUT~reg0 } "NODE_NAME" } } { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 25 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.234 ns ( 32.23 % ) " "Info: Total cell delay = 0.234 ns ( 32.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.492 ns ( 67.77 % ) " "Info: Total interconnect delay = 0.492 ns ( 67.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.726 ns" { REGISTER[0] PNOUT~63 PNOUT~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.726 ns" { REGISTER[0] {} PNOUT~63 {} PNOUT~reg0 {} } { 0.000ns 0.492ns 0.000ns } { 0.000ns 0.150ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.777 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.777 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns CLK 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'CLK'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.117 ns) + CELL(0.000 ns) 1.096 ns CLK~clkctrl 2 COMB CLKCTRL_G3 19 " "Info: 2: + IC(0.117 ns) + CELL(0.000 ns) = 1.096 ns; Loc. = CLKCTRL_G3; Fanout = 19; COMB Node = 'CLK~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.117 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.144 ns) + CELL(0.537 ns) 2.777 ns PNOUT~reg0 3 REG LCFF_X75_Y1_N17 2 " "Info: 3: + IC(1.144 ns) + CELL(0.537 ns) = 2.777 ns; Loc. = LCFF_X75_Y1_N17; Fanout = 2; REG Node = 'PNOUT~reg0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.681 ns" { CLK~clkctrl PNOUT~reg0 } "NODE_NAME" } } { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 25 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.516 ns ( 54.59 % ) " "Info: Total cell delay = 1.516 ns ( 54.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.261 ns ( 45.41 % ) " "Info: Total interconnect delay = 1.261 ns ( 45.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.777 ns" { CLK CLK~clkctrl PNOUT~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.777 ns" { CLK {} CLK~combout {} CLK~clkctrl {} PNOUT~reg0 {} } { 0.000ns 0.000ns 0.117ns 1.144ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.777 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 2.777 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns CLK 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'CLK'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.117 ns) + CELL(0.000 ns) 1.096 ns CLK~clkctrl 2 COMB CLKCTRL_G3 19 " "Info: 2: + IC(0.117 ns) + CELL(0.000 ns) = 1.096 ns; Loc. = CLKCTRL_G3; Fanout = 19; COMB Node = 'CLK~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.117 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.144 ns) + CELL(0.537 ns) 2.777 ns REGISTER\[0\] 3 REG LCFF_X75_Y1_N21 2 " "Info: 3: + IC(1.144 ns) + CELL(0.537 ns) = 2.777 ns; Loc. = LCFF_X75_Y1_N21; Fanout = 2; REG Node = 'REGISTER\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.681 ns" { CLK~clkctrl REGISTER[0] } "NODE_NAME" } } { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.516 ns ( 54.59 % ) " "Info: Total cell delay = 1.516 ns ( 54.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.261 ns ( 45.41 % ) " "Info: Total interconnect delay = 1.261 ns ( 45.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.777 ns" { CLK CLK~clkctrl REGISTER[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.777 ns" { CLK {} CLK~combout {} CLK~clkctrl {} REGISTER[0] {} } { 0.000ns 0.000ns 0.117ns 1.144ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.777 ns" { CLK CLK~clkctrl PNOUT~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.777 ns" { CLK {} CLK~combout {} CLK~clkctrl {} PNOUT~reg0 {} } { 0.000ns 0.000ns 0.117ns 1.144ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.777 ns" { CLK CLK~clkctrl REGISTER[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.777 ns" { CLK {} CLK~combout {} CLK~clkctrl {} REGISTER[0] {} } { 0.000ns 0.000ns 0.117ns 1.144ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 25 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 25 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.726 ns" { REGISTER[0] PNOUT~63 PNOUT~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.726 ns" { REGISTER[0] {} PNOUT~63 {} PNOUT~reg0 {} } { 0.000ns 0.492ns 0.000ns } { 0.000ns 0.150ns 0.084ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.777 ns" { CLK CLK~clkctrl PNOUT~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.777 ns" { CLK {} CLK~combout {} CLK~clkctrl {} PNOUT~reg0 {} } { 0.000ns 0.000ns 0.117ns 1.144ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.777 ns" { CLK CLK~clkctrl REGISTER[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.777 ns" { CLK {} CLK~combout {} CLK~clkctrl {} REGISTER[0] {} } { 0.000ns 0.000ns 0.117ns 1.144ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { PNOUT~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { PNOUT~reg0 {} } {  } {  } "" } } { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 25 0 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "REGISTER\[0\] OUTEN CLK 3.456 ns register " "Info: tsu for register \"REGISTER\[0\]\" (data pin = \"OUTEN\", clock pin = \"CLK\") is 3.456 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.269 ns + Longest pin register " "Info: + Longest pin to register delay is 6.269 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.820 ns) 0.820 ns OUTEN 1 PIN PIN_Y17 19 " "Info: 1: + IC(0.000 ns) + CELL(0.820 ns) = 0.820 ns; Loc. = PIN_Y17; Fanout = 19; PIN Node = 'OUTEN'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { OUTEN } "NODE_NAME" } } { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.789 ns) + CELL(0.660 ns) 6.269 ns REGISTER\[0\] 2 REG LCFF_X75_Y1_N21 2 " "Info: 2: + IC(4.789 ns) + CELL(0.660 ns) = 6.269 ns; Loc. = LCFF_X75_Y1_N21; Fanout = 2; REG Node = 'REGISTER\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.449 ns" { OUTEN REGISTER[0] } "NODE_NAME" } } { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.480 ns ( 23.61 % ) " "Info: Total cell delay = 1.480 ns ( 23.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.789 ns ( 76.39 % ) " "Info: Total interconnect delay = 4.789 ns ( 76.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.269 ns" { OUTEN REGISTER[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.269 ns" { OUTEN {} OUTEN~combout {} REGISTER[0] {} } { 0.000ns 0.000ns 4.789ns } { 0.000ns 0.820ns 0.660ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 25 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.777 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 2.777 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns CLK 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'CLK'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.117 ns) + CELL(0.000 ns) 1.096 ns CLK~clkctrl 2 COMB CLKCTRL_G3 19 " "Info: 2: + IC(0.117 ns) + CELL(0.000 ns) = 1.096 ns; Loc. = CLKCTRL_G3; Fanout = 19; COMB Node = 'CLK~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.117 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.144 ns) + CELL(0.537 ns) 2.777 ns REGISTER\[0\] 3 REG LCFF_X75_Y1_N21 2 " "Info: 3: + IC(1.144 ns) + CELL(0.537 ns) = 2.777 ns; Loc. = LCFF_X75_Y1_N21; Fanout = 2; REG Node = 'REGISTER\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.681 ns" { CLK~clkctrl REGISTER[0] } "NODE_NAME" } } { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.516 ns ( 54.59 % ) " "Info: Total cell delay = 1.516 ns ( 54.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.261 ns ( 45.41 % ) " "Info: Total interconnect delay = 1.261 ns ( 45.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.777 ns" { CLK CLK~clkctrl REGISTER[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.777 ns" { CLK {} CLK~combout {} CLK~clkctrl {} REGISTER[0] {} } { 0.000ns 0.000ns 0.117ns 1.144ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.269 ns" { OUTEN REGISTER[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.269 ns" { OUTEN {} OUTEN~combout {} REGISTER[0] {} } { 0.000ns 0.000ns 4.789ns } { 0.000ns 0.820ns 0.660ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.777 ns" { CLK CLK~clkctrl REGISTER[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.777 ns" { CLK {} CLK~combout {} CLK~clkctrl {} REGISTER[0] {} } { 0.000ns 0.000ns 0.117ns 1.144ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK PNOUT PNOUT~reg0 6.429 ns register " "Info: tco from clock \"CLK\" to destination pin \"PNOUT\" through register \"PNOUT~reg0\" is 6.429 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.777 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 2.777 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns CLK 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'CLK'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.117 ns) + CELL(0.000 ns) 1.096 ns CLK~clkctrl 2 COMB CLKCTRL_G3 19 " "Info: 2: + IC(0.117 ns) + CELL(0.000 ns) = 1.096 ns; Loc. = CLKCTRL_G3; Fanout = 19; COMB Node = 'CLK~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.117 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.144 ns) + CELL(0.537 ns) 2.777 ns PNOUT~reg0 3 REG LCFF_X75_Y1_N17 2 " "Info: 3: + IC(1.144 ns) + CELL(0.537 ns) = 2.777 ns; Loc. = LCFF_X75_Y1_N17; Fanout = 2; REG Node = 'PNOUT~reg0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.681 ns" { CLK~clkctrl PNOUT~reg0 } "NODE_NAME" } } { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 25 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.516 ns ( 54.59 % ) " "Info: Total cell delay = 1.516 ns ( 54.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.261 ns ( 45.41 % ) " "Info: Total interconnect delay = 1.261 ns ( 45.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.777 ns" { CLK CLK~clkctrl PNOUT~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.777 ns" { CLK {} CLK~combout {} CLK~clkctrl {} PNOUT~reg0 {} } { 0.000ns 0.000ns 0.117ns 1.144ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 25 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.402 ns + Longest register pin " "Info: + Longest register to pin delay is 3.402 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PNOUT~reg0 1 REG LCFF_X75_Y1_N17 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X75_Y1_N17; Fanout = 2; REG Node = 'PNOUT~reg0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { PNOUT~reg0 } "NODE_NAME" } } { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 25 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.624 ns) + CELL(2.778 ns) 3.402 ns PNOUT 2 PIN PIN_V15 0 " "Info: 2: + IC(0.624 ns) + CELL(2.778 ns) = 3.402 ns; Loc. = PIN_V15; Fanout = 0; PIN Node = 'PNOUT'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.402 ns" { PNOUT~reg0 PNOUT } "NODE_NAME" } } { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.778 ns ( 81.66 % ) " "Info: Total cell delay = 2.778 ns ( 81.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.624 ns ( 18.34 % ) " "Info: Total interconnect delay = 0.624 ns ( 18.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.402 ns" { PNOUT~reg0 PNOUT } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.402 ns" { PNOUT~reg0 {} PNOUT {} } { 0.000ns 0.624ns } { 0.000ns 2.778ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.777 ns" { CLK CLK~clkctrl PNOUT~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.777 ns" { CLK {} CLK~combout {} CLK~clkctrl {} PNOUT~reg0 {} } { 0.000ns 0.000ns 0.117ns 1.144ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.402 ns" { PNOUT~reg0 PNOUT } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.402 ns" { PNOUT~reg0 {} PNOUT {} } { 0.000ns 0.624ns } { 0.000ns 2.778ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "PNOUT~reg0 RST CLK -1.668 ns register " "Info: th for register \"PNOUT~reg0\" (data pin = \"RST\", clock pin = \"CLK\") is -1.668 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.777 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 2.777 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns CLK 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'CLK'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.117 ns) + CELL(0.000 ns) 1.096 ns CLK~clkctrl 2 COMB CLKCTRL_G3 19 " "Info: 2: + IC(0.117 ns) + CELL(0.000 ns) = 1.096 ns; Loc. = CLKCTRL_G3; Fanout = 19; COMB Node = 'CLK~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.117 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.144 ns) + CELL(0.537 ns) 2.777 ns PNOUT~reg0 3 REG LCFF_X75_Y1_N17 2 " "Info: 3: + IC(1.144 ns) + CELL(0.537 ns) = 2.777 ns; Loc. = LCFF_X75_Y1_N17; Fanout = 2; REG Node = 'PNOUT~reg0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.681 ns" { CLK~clkctrl PNOUT~reg0 } "NODE_NAME" } } { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 25 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.516 ns ( 54.59 % ) " "Info: Total cell delay = 1.516 ns ( 54.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.261 ns ( 45.41 % ) " "Info: Total interconnect delay = 1.261 ns ( 45.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.777 ns" { CLK CLK~clkctrl PNOUT~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.777 ns" { CLK {} CLK~combout {} CLK~clkctrl {} PNOUT~reg0 {} } { 0.000ns 0.000ns 0.117ns 1.144ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 25 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.711 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.711 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns RST 1 PIN PIN_M2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_M2; Fanout = 2; PIN Node = 'RST'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { RST } "NODE_NAME" } } { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.229 ns) + CELL(0.419 ns) 4.627 ns PNOUT~63 2 COMB LCCOMB_X75_Y1_N16 1 " "Info: 2: + IC(3.229 ns) + CELL(0.419 ns) = 4.627 ns; Loc. = LCCOMB_X75_Y1_N16; Fanout = 1; COMB Node = 'PNOUT~63'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.648 ns" { RST PNOUT~63 } "NODE_NAME" } } { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 4.711 ns PNOUT~reg0 3 REG LCFF_X75_Y1_N17 2 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 4.711 ns; Loc. = LCFF_X75_Y1_N17; Fanout = 2; REG Node = 'PNOUT~reg0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { PNOUT~63 PNOUT~reg0 } "NODE_NAME" } } { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 25 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.482 ns ( 31.46 % ) " "Info: Total cell delay = 1.482 ns ( 31.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.229 ns ( 68.54 % ) " "Info: Total interconnect delay = 3.229 ns ( 68.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.711 ns" { RST PNOUT~63 PNOUT~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.711 ns" { RST {} RST~combout {} PNOUT~63 {} PNOUT~reg0 {} } { 0.000ns 0.000ns 3.229ns 0.000ns } { 0.000ns 0.979ns 0.419ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.777 ns" { CLK CLK~clkctrl PNOUT~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.777 ns" { CLK {} CLK~combout {} CLK~clkctrl {} PNOUT~reg0 {} } { 0.000ns 0.000ns 0.117ns 1.144ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.711 ns" { RST PNOUT~63 PNOUT~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.711 ns" { RST {} RST~combout {} PNOUT~63 {} PNOUT~reg0 {} } { 0.000ns 0.000ns 3.229ns 0.000ns } { 0.000ns 0.979ns 0.419ns 0.084ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}