prev_cmp_pngenchuan_18.qmsg

生成18级的m序列的VerilogHDL程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Simulator Quartus II " "Info: Running Quartus II Simulator" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jan 23 15:59:20 2008 " "Info: Processing started: Wed Jan 23 15:59:20 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sim --read_settings_files=on --write_settings_files=off PNGENchuan_18 -c PNGENchuan_18 " "Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off PNGENchuan_18 -c PNGENchuan_18" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISDB_SOURCE_VECTOR_FILE_USED" "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.vwf " "Info: Using vector source file \"E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.vwf\"" {  } {  } 0 0 "Using vector source file \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_FOUND" "" "Info: Inverted registers were found during simulation" { { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|PNGENchuan_18\|REGISTER\[0\] " "Info: Register: \|PNGENchuan_18\|REGISTER\[0\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|PNGENchuan_18\|REGISTER\[17\] " "Info: Register: \|PNGENchuan_18\|REGISTER\[17\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|PNGENchuan_18\|REGISTER\[6\] " "Info: Register: \|PNGENchuan_18\|REGISTER\[6\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|PNGENchuan_18\|REGISTER\[16\] " "Info: Register: \|PNGENchuan_18\|REGISTER\[16\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|PNGENchuan_18\|REGISTER\[5\] " "Info: Register: \|PNGENchuan_18\|REGISTER\[5\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|PNGENchuan_18\|REGISTER\[15\] " "Info: Register: \|PNGENchuan_18\|REGISTER\[15\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|PNGENchuan_18\|REGISTER\[4\] " "Info: Register: \|PNGENchuan_18\|REGISTER\[4\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|PNGENchuan_18\|REGISTER\[14\] " "Info: Register: \|PNGENchuan_18\|REGISTER\[14\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|PNGENchuan_18\|REGISTER\[3\] " "Info: Register: \|PNGENchuan_18\|REGISTER\[3\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|PNGENchuan_18\|REGISTER\[13\] " "Info: Register: \|PNGENchuan_18\|REGISTER\[13\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|PNGENchuan_18\|REGISTER\[2\] " "Info: Register: \|PNGENchuan_18\|REGISTER\[2\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|PNGENchuan_18\|REGISTER\[12\] " "Info: Register: \|PNGENchuan_18\|REGISTER\[12\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|PNGENchuan_18\|REGISTER\[1\] " "Info: Register: \|PNGENchuan_18\|REGISTER\[1\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|PNGENchuan_18\|REGISTER\[11\] " "Info: Register: \|PNGENchuan_18\|REGISTER\[11\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|PNGENchuan_18\|REGISTER\[10\] " "Info: Register: \|PNGENchuan_18\|REGISTER\[10\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|PNGENchuan_18\|REGISTER\[9\] " "Info: Register: \|PNGENchuan_18\|REGISTER\[9\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|PNGENchuan_18\|REGISTER\[8\] " "Info: Register: \|PNGENchuan_18\|REGISTER\[8\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|PNGENchuan_18\|REGISTER\[7\] " "Info: Register: \|PNGENchuan_18\|REGISTER\[7\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0}  } {  } 0 0 "Inverted registers were found during simulation" 0 0 "" 0}
{ "Info" "IEDS_MAX_TRANSITION_COUNT" "" "Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled" { { "Info" "IEDS_MAX_TRANSITION_COUNT_EXP" "" "Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." {  } {  } 0 0 "Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." 0 0 "" 0}  } {  } 0 0 "Option to preserve fewer signal transitions to reduce memory requirements is enabled" 0 0 "" 0}
{ "Info" "IEDS_SUB_SIMULATION_COUNT" "1 " "Info: Simulation partitioned into 1 sub-simulations" {  } {  } 0 0 "Simulation partitioned into %1!d! sub-simulations" 0 0 "" 0}
{ "Info" "ISIM_SIM_SIMULATION_COVERAGE" "     97.56 % " "Info: Simulation coverage is      97.56 %" {  } {  } 0 0 "Simulation coverage is %1!s!" 0 0 "" 0}
{ "Info" "ISIM_SIM_NUMBER_OF_TRANSITION" "129987 " "Info: Number of transitions in simulation is 129987" {  } {  } 0 0 "Number of transitions in simulation is %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Simulator 0 s 0 s Quartus II " "Info: Quartus II Simulator was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "104 " "Info: Allocated 104 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jan 23 15:59:23 2008 " "Info: Processing ended: Wed Jan 23 15:59:23 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}