📄 pngenchuan_18_v.sdo

📁 生成18级的m序列的VerilogHDL程序
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    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE REGISTER\[9\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1681:1681:1681) (1681:1681:1681))
        (PORT datain (84:84:84) (84:84:84))
        (PORT aclr (1684:1684:1684) (1684:1684:1684))
        (PORT ena (5449:5449:5449) (5449:5449:5449))
        (IOPATH (posedge clk) regout (250:250:250) (250:250:250))
        (IOPATH (posedge aclr) regout (218:218:218) (218:218:218))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (266:266:266))
      (HOLD ena (posedge clk) (266:266:266))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE REGISTER\[10\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (299:299:299) (299:299:299))
        (IOPATH datad combout (149:149:149) (149:149:149))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE REGISTER\[10\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1681:1681:1681) (1681:1681:1681))
        (PORT datain (84:84:84) (84:84:84))
        (PORT aclr (1684:1684:1684) (1684:1684:1684))
        (PORT ena (5449:5449:5449) (5449:5449:5449))
        (IOPATH (posedge clk) regout (250:250:250) (250:250:250))
        (IOPATH (posedge aclr) regout (218:218:218) (218:218:218))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (266:266:266))
      (HOLD ena (posedge clk) (266:266:266))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE REGISTER\[11\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (305:305:305) (305:305:305))
        (IOPATH datad combout (149:149:149) (149:149:149))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE REGISTER\[11\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1681:1681:1681) (1681:1681:1681))
        (PORT datain (84:84:84) (84:84:84))
        (PORT aclr (1684:1684:1684) (1684:1684:1684))
        (PORT ena (5449:5449:5449) (5449:5449:5449))
        (IOPATH (posedge clk) regout (250:250:250) (250:250:250))
        (IOPATH (posedge aclr) regout (218:218:218) (218:218:218))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (266:266:266))
      (HOLD ena (posedge clk) (266:266:266))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE REGISTER\[12\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (438:438:438) (438:438:438))
        (IOPATH datad combout (149:149:149) (149:149:149))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE REGISTER\[12\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1681:1681:1681) (1681:1681:1681))
        (PORT datain (84:84:84) (84:84:84))
        (PORT aclr (1684:1684:1684) (1684:1684:1684))
        (PORT ena (5439:5439:5439) (5439:5439:5439))
        (IOPATH (posedge clk) regout (250:250:250) (250:250:250))
        (IOPATH (posedge aclr) regout (218:218:218) (218:218:218))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (266:266:266))
      (HOLD ena (posedge clk) (266:266:266))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE REGISTER\[13\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (295:295:295) (295:295:295))
        (IOPATH datad combout (149:149:149) (149:149:149))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE REGISTER\[13\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1681:1681:1681) (1681:1681:1681))
        (PORT datain (84:84:84) (84:84:84))
        (PORT aclr (1684:1684:1684) (1684:1684:1684))
        (PORT ena (5439:5439:5439) (5439:5439:5439))
        (IOPATH (posedge clk) regout (250:250:250) (250:250:250))
        (IOPATH (posedge aclr) regout (218:218:218) (218:218:218))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (266:266:266))
      (HOLD ena (posedge clk) (266:266:266))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE REGISTER\[14\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (299:299:299) (299:299:299))
        (IOPATH datad combout (149:149:149) (149:149:149))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE REGISTER\[14\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1681:1681:1681) (1681:1681:1681))
        (PORT datain (84:84:84) (84:84:84))
        (PORT aclr (1684:1684:1684) (1684:1684:1684))
        (PORT ena (5439:5439:5439) (5439:5439:5439))
        (IOPATH (posedge clk) regout (250:250:250) (250:250:250))
        (IOPATH (posedge aclr) regout (218:218:218) (218:218:218))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (266:266:266))
      (HOLD ena (posedge clk) (266:266:266))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE REGISTER\[15\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (445:445:445) (445:445:445))
        (IOPATH datad combout (149:149:149) (149:149:149))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE REGISTER\[15\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1681:1681:1681) (1681:1681:1681))
        (PORT datain (84:84:84) (84:84:84))
        (PORT aclr (1684:1684:1684) (1684:1684:1684))
        (PORT ena (5449:5449:5449) (5449:5449:5449))
        (IOPATH (posedge clk) regout (250:250:250) (250:250:250))
        (IOPATH (posedge aclr) regout (218:218:218) (218:218:218))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (266:266:266))
      (HOLD ena (posedge clk) (266:266:266))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE REGISTER\[16\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (306:306:306) (306:306:306))
        (IOPATH datad combout (149:149:149) (149:149:149))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE REGISTER\[16\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1681:1681:1681) (1681:1681:1681))
        (PORT datain (84:84:84) (84:84:84))
        (PORT aclr (1684:1684:1684) (1684:1684:1684))
        (PORT ena (5449:5449:5449) (5449:5449:5449))
        (IOPATH (posedge clk) regout (250:250:250) (250:250:250))
        (IOPATH (posedge aclr) regout (218:218:218) (218:218:218))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (266:266:266))
      (HOLD ena (posedge clk) (266:266:266))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE REGISTER\[17\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (307:307:307) (307:307:307))
        (IOPATH datad combout (149:149:149) (149:149:149))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE REGISTER\[17\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1681:1681:1681) (1681:1681:1681))
        (PORT datain (84:84:84) (84:84:84))
        (PORT aclr (1684:1684:1684) (1684:1684:1684))
        (PORT ena (5449:5449:5449) (5449:5449:5449))
        (IOPATH (posedge clk) regout (250:250:250) (250:250:250))
        (IOPATH (posedge aclr) regout (218:218:218) (218:218:218))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (266:266:266))
      (HOLD ena (posedge clk) (266:266:266))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE REGISTER\~0)
    (DELAY
      (ABSOLUTE
        (PORT datac (312:312:312) (312:312:312))
        (PORT datad (488:488:488) (488:488:488))
        (IOPATH datac combout (271:271:271) (271:271:271))
        (IOPATH datad combout (150:150:150) (150:150:150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE REGISTER\[0\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1681:1681:1681) (1681:1681:1681))
        (PORT datain (84:84:84) (84:84:84))
        (PORT aclr (1684:1684:1684) (1684:1684:1684))
        (PORT ena (5449:5449:5449) (5449:5449:5449))
        (IOPATH (posedge clk) regout (250:250:250) (250:250:250))
        (IOPATH (posedge aclr) regout (218:218:218) (218:218:218))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (266:266:266))
      (HOLD ena (posedge clk) (266:266:266))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE PNOUT\~63)
    (DELAY
      (ABSOLUTE
        (PORT dataa (4828:4828:4828) (4828:4828:4828))
        (PORT datab (3229:3229:3229) (3229:3229:3229))
        (PORT datad (492:492:492) (492:492:492))
        (IOPATH dataa combout (438:438:438) (438:438:438))
        (IOPATH datab combout (419:419:419) (419:419:419))
        (IOPATH datac combout (323:323:323) (323:323:323))
        (IOPATH datad combout (150:150:150) (150:150:150))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE PNOUT\~reg0)
    (DELAY
      (ABSOLUTE
        (PORT clk (1681:1681:1681) (1681:1681:1681))
        (PORT datain (84:84:84) (84:84:84))
        (IOPATH (posedge clk) regout (250:250:250) (250:250:250))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (266:266:266))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_asynch_io")
    (INSTANCE PNOUT\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (PORT datain (624:624:624) (624:624:624))
        (IOPATH datain padio (2778:2778:2778) (2778:2778:2778))
      )
    )
  )
)
上一页 12
💿 文件大小 235 K
👤 上传用户 teasler111
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#VerilogHDL #序列 #程序
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