pngenchuan_18_v.sdo

生成18级的m序列的VerilogHDL程序

// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// 
// Device: Altera EP2C50F484C6 Package FBGA484
// 

// 
// This SDF file should be used for ModelSim (Verilog) only
// 

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "PNGENchuan_18")
  (DATE "01/23/2008 15:55:16")
  (VENDOR "Altera")
  (PROGRAM "Quartus II")
  (VERSION "Version 7.2 Build 151 09/26/2007 SJ Full Version")
  (DIVIDER .)
  (TIMESCALE 1 ps)

  (CELL
    (CELLTYPE "cycloneii_asynch_io")
    (INSTANCE CLK\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (979:979:979) (979:979:979))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_clkctrl")
    (INSTANCE CLK\~clkctrl)
    (DELAY
      (ABSOLUTE
        (PORT inclk[0] (117:117:117) (117:117:117))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ena_reg")
    (INSTANCE CLK\~clkctrl.extena0_reg)
    (DELAY
      (ABSOLUTE
        (PORT d (253:253:253) (253:253:253))
        (PORT clk (0:0:0) (0:0:0))
        (IOPATH (posedge clk) q (218:218:218) (218:218:218))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (50:50:50))
      (HOLD d (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_asynch_io")
    (INSTANCE RST\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (979:979:979) (979:979:979))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_clkctrl")
    (INSTANCE RST\~clkctrl)
    (DELAY
      (ABSOLUTE
        (PORT inclk[0] (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ena_reg")
    (INSTANCE RST\~clkctrl.extena0_reg)
    (DELAY
      (ABSOLUTE
        (PORT d (253:253:253) (253:253:253))
        (PORT clk (0:0:0) (0:0:0))
        (IOPATH (posedge clk) q (218:218:218) (218:218:218))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (50:50:50))
      (HOLD d (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_asynch_io")
    (INSTANCE OUTEN\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (820:820:820) (820:820:820))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE REGISTER\[1\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1681:1681:1681) (1681:1681:1681))
        (PORT sdata (686:686:686) (686:686:686))
        (PORT aclr (1684:1684:1684) (1684:1684:1684))
        (PORT ena (5449:5449:5449) (5449:5449:5449))
        (IOPATH (posedge clk) regout (250:250:250) (250:250:250))
        (IOPATH (posedge aclr) regout (218:218:218) (218:218:218))
      )
    )
    (TIMINGCHECK
      (HOLD sdata (posedge clk) (266:266:266))
      (HOLD ena (posedge clk) (266:266:266))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE REGISTER\[2\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (305:305:305) (305:305:305))
        (IOPATH datad combout (149:149:149) (149:149:149))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE REGISTER\[2\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1681:1681:1681) (1681:1681:1681))
        (PORT datain (84:84:84) (84:84:84))
        (PORT aclr (1684:1684:1684) (1684:1684:1684))
        (PORT ena (5449:5449:5449) (5449:5449:5449))
        (IOPATH (posedge clk) regout (250:250:250) (250:250:250))
        (IOPATH (posedge aclr) regout (218:218:218) (218:218:218))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (266:266:266))
      (HOLD ena (posedge clk) (266:266:266))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE REGISTER\[3\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (307:307:307) (307:307:307))
        (IOPATH datad combout (149:149:149) (149:149:149))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE REGISTER\[3\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1681:1681:1681) (1681:1681:1681))
        (PORT datain (84:84:84) (84:84:84))
        (PORT aclr (1684:1684:1684) (1684:1684:1684))
        (PORT ena (5449:5449:5449) (5449:5449:5449))
        (IOPATH (posedge clk) regout (250:250:250) (250:250:250))
        (IOPATH (posedge aclr) regout (218:218:218) (218:218:218))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (266:266:266))
      (HOLD ena (posedge clk) (266:266:266))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE REGISTER\[4\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1681:1681:1681) (1681:1681:1681))
        (PORT sdata (676:676:676) (676:676:676))
        (PORT aclr (1684:1684:1684) (1684:1684:1684))
        (PORT ena (5449:5449:5449) (5449:5449:5449))
        (IOPATH (posedge clk) regout (250:250:250) (250:250:250))
        (IOPATH (posedge aclr) regout (218:218:218) (218:218:218))
      )
    )
    (TIMINGCHECK
      (HOLD sdata (posedge clk) (266:266:266))
      (HOLD ena (posedge clk) (266:266:266))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE REGISTER\[5\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (305:305:305) (305:305:305))
        (IOPATH datad combout (149:149:149) (149:149:149))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE REGISTER\[5\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1681:1681:1681) (1681:1681:1681))
        (PORT datain (84:84:84) (84:84:84))
        (PORT aclr (1684:1684:1684) (1684:1684:1684))
        (PORT ena (5449:5449:5449) (5449:5449:5449))
        (IOPATH (posedge clk) regout (250:250:250) (250:250:250))
        (IOPATH (posedge aclr) regout (218:218:218) (218:218:218))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (266:266:266))
      (HOLD ena (posedge clk) (266:266:266))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE REGISTER\[6\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (307:307:307) (307:307:307))
        (IOPATH datad combout (149:149:149) (149:149:149))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE REGISTER\[6\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1681:1681:1681) (1681:1681:1681))
        (PORT datain (84:84:84) (84:84:84))
        (PORT aclr (1684:1684:1684) (1684:1684:1684))
        (PORT ena (5449:5449:5449) (5449:5449:5449))
        (IOPATH (posedge clk) regout (250:250:250) (250:250:250))
        (IOPATH (posedge aclr) regout (218:218:218) (218:218:218))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (266:266:266))
      (HOLD ena (posedge clk) (266:266:266))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE REGISTER\[7\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1681:1681:1681) (1681:1681:1681))
        (PORT sdata (683:683:683) (683:683:683))
        (PORT aclr (1684:1684:1684) (1684:1684:1684))
        (PORT ena (5449:5449:5449) (5449:5449:5449))
        (IOPATH (posedge clk) regout (250:250:250) (250:250:250))
        (IOPATH (posedge aclr) regout (218:218:218) (218:218:218))
      )
    )
    (TIMINGCHECK
      (HOLD sdata (posedge clk) (266:266:266))
      (HOLD ena (posedge clk) (266:266:266))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE REGISTER\[8\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (308:308:308) (308:308:308))
        (IOPATH datad combout (149:149:149) (149:149:149))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE REGISTER\[8\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1681:1681:1681) (1681:1681:1681))
        (PORT datain (84:84:84) (84:84:84))
        (PORT aclr (1684:1684:1684) (1684:1684:1684))
        (PORT ena (5449:5449:5449) (5449:5449:5449))
        (IOPATH (posedge clk) regout (250:250:250) (250:250:250))
        (IOPATH (posedge aclr) regout (218:218:218) (218:218:218))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (266:266:266))
      (HOLD ena (posedge clk) (266:266:266))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE REGISTER\[9\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (308:308:308) (308:308:308))
        (IOPATH datad combout (149:149:149) (149:149:149))
      )
    )
  )
  (CELL