pngenchuan_18.vo

生成18级的m序列的VerilogHDL程序

// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 7.2 Build 151 09/26/2007 SJ Full Version"

// DATE "01/23/2008 15:55:16"

// 
// Device: Altera EP2C50F484C6 Package FBGA484
// 

// 
// This Verilog file should be used for ModelSim (Verilog) only
// 

`timescale 1 ps/ 1 ps

module PNGENchuan_18 (
	RST,
	CLK,
	PNOUT,
	OUTEN);
input 	RST;
input 	CLK;
output 	PNOUT;
input 	OUTEN;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri1 devoe;
// synopsys translate_off
initial $sdf_annotate("PNGENchuan_18_v.sdo");
// synopsys translate_on

wire \CLK~combout ;
wire \CLK~clkctrl_outclk ;
wire \RST~combout ;
wire \RST~clkctrl_outclk ;
wire \OUTEN~combout ;
wire \REGISTER[2]~feeder_combout ;
wire \REGISTER[3]~feeder_combout ;
wire \REGISTER[5]~feeder_combout ;
wire \REGISTER[6]~feeder_combout ;
wire \REGISTER[8]~feeder_combout ;
wire \REGISTER[9]~feeder_combout ;
wire \REGISTER[10]~feeder_combout ;
wire \REGISTER[11]~feeder_combout ;
wire \REGISTER[12]~feeder_combout ;
wire \REGISTER[13]~feeder_combout ;
wire \REGISTER[14]~feeder_combout ;
wire \REGISTER[15]~feeder_combout ;
wire \REGISTER[16]~feeder_combout ;
wire \REGISTER[17]~feeder_combout ;
wire \REGISTER~0_combout ;
wire \PNOUT~63_combout ;
wire \PNOUT~reg0_regout ;
wire [17:0] REGISTER;


// atom is at PIN_M1
cycloneii_io \CLK~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\CLK~combout ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(CLK));
// synopsys translate_off
defparam \CLK~I .input_async_reset = "none";
defparam \CLK~I .input_power_up = "low";
defparam \CLK~I .input_register_mode = "none";
defparam \CLK~I .input_sync_reset = "none";
defparam \CLK~I .oe_async_reset = "none";
defparam \CLK~I .oe_power_up = "low";
defparam \CLK~I .oe_register_mode = "none";
defparam \CLK~I .oe_sync_reset = "none";
defparam \CLK~I .operation_mode = "input";
defparam \CLK~I .output_async_reset = "none";
defparam \CLK~I .output_power_up = "low";
defparam \CLK~I .output_register_mode = "none";
defparam \CLK~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at CLKCTRL_G3
cycloneii_clkctrl \CLK~clkctrl (
	.ena(vcc),
	.inclk({gnd,gnd,gnd,\CLK~combout }),
	.clkselect(2'b00),
	.devclrn(devclrn),
	.devpor(devpor),
	.outclk(\CLK~clkctrl_outclk ));
// synopsys translate_off
defparam \CLK~clkctrl .clock_type = "global clock";
defparam \CLK~clkctrl .ena_register_mode = "falling edge";
// synopsys translate_on

// atom is at PIN_M2
cycloneii_io \RST~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\RST~combout ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(RST));
// synopsys translate_off
defparam \RST~I .input_async_reset = "none";
defparam \RST~I .input_power_up = "low";
defparam \RST~I .input_register_mode = "none";
defparam \RST~I .input_sync_reset = "none";
defparam \RST~I .oe_async_reset = "none";
defparam \RST~I .oe_power_up = "low";
defparam \RST~I .oe_register_mode = "none";
defparam \RST~I .oe_sync_reset = "none";
defparam \RST~I .operation_mode = "input";
defparam \RST~I .output_async_reset = "none";
defparam \RST~I .output_power_up = "low";
defparam \RST~I .output_register_mode = "none";
defparam \RST~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at CLKCTRL_G1
cycloneii_clkctrl \RST~clkctrl (
	.ena(vcc),
	.inclk({gnd,gnd,gnd,\RST~combout }),
	.clkselect(2'b00),
	.devclrn(devclrn),
	.devpor(devpor),
	.outclk(\RST~clkctrl_outclk ));
// synopsys translate_off
defparam \RST~clkctrl .clock_type = "global clock";
defparam \RST~clkctrl .ena_register_mode = "falling edge";
// synopsys translate_on

// atom is at PIN_Y17
cycloneii_io \OUTEN~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\OUTEN~combout ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(OUTEN));
// synopsys translate_off
defparam \OUTEN~I .input_async_reset = "none";
defparam \OUTEN~I .input_power_up = "low";
defparam \OUTEN~I .input_register_mode = "none";
defparam \OUTEN~I .input_sync_reset = "none";
defparam \OUTEN~I .oe_async_reset = "none";
defparam \OUTEN~I .oe_power_up = "low";
defparam \OUTEN~I .oe_register_mode = "none";
defparam \OUTEN~I .oe_sync_reset = "none";
defparam \OUTEN~I .operation_mode = "input";
defparam \OUTEN~I .output_async_reset = "none";
defparam \OUTEN~I .output_power_up = "low";
defparam \OUTEN~I .output_register_mode = "none";
defparam \OUTEN~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LCFF_X75_Y1_N7
cycloneii_lcell_ff \REGISTER[1] (
	.clk(\CLK~clkctrl_outclk ),
	.datain(gnd),
	.sdata(REGISTER[0]),
	.aclr(\RST~clkctrl_outclk ),
	.sclr(gnd),
	.sload(vcc),
	.ena(\OUTEN~combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(REGISTER[1]));

// atom is at LCCOMB_X75_Y1_N10
cycloneii_lcell_comb \REGISTER[2]~feeder (
// Equation(s):
// \REGISTER[2]~feeder_combout  = REGISTER[1]

	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(REGISTER[1]),
	.cin(gnd),
	.combout(\REGISTER[2]~feeder_combout ),
	.cout());
// synopsys translate_off
defparam \REGISTER[2]~feeder .lut_mask = 16'hFF00;
defparam \REGISTER[2]~feeder .sum_lutc_input = "datac";
// synopsys translate_on

// atom is at LCFF_X75_Y1_N11
cycloneii_lcell_ff \REGISTER[2] (
	.clk(\CLK~clkctrl_outclk ),
	.datain(\REGISTER[2]~feeder_combout ),
	.sdata(gnd),
	.aclr(\RST~clkctrl_outclk ),
	.sclr(gnd),
	.sload(gnd),
	.ena(\OUTEN~combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(REGISTER[2]));

// atom is at LCCOMB_X75_Y1_N24
cycloneii_lcell_comb \REGISTER[3]~feeder (
// Equation(s):
// \REGISTER[3]~feeder_combout  = REGISTER[2]

	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(REGISTER[2]),
	.cin(gnd),
	.combout(\REGISTER[3]~feeder_combout ),
	.cout());
// synopsys translate_off
defparam \REGISTER[3]~feeder .lut_mask = 16'hFF00;
defparam \REGISTER[3]~feeder .sum_lutc_input = "datac";
// synopsys translate_on

// atom is at LCFF_X75_Y1_N25
cycloneii_lcell_ff \REGISTER[3] (
	.clk(\CLK~clkctrl_outclk ),
	.datain(\REGISTER[3]~feeder_combout ),
	.sdata(gnd),
	.aclr(\RST~clkctrl_outclk ),
	.sclr(gnd),
	.sload(gnd),
	.ena(\OUTEN~combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(REGISTER[3]));

// atom is at LCFF_X75_Y1_N19
cycloneii_lcell_ff \REGISTER[4] (
	.clk(\CLK~clkctrl_outclk ),
	.datain(gnd),
	.sdata(REGISTER[3]),
	.aclr(\RST~clkctrl_outclk ),
	.sclr(gnd),
	.sload(vcc),
	.ena(\OUTEN~combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(REGISTER[4]));

// atom is at LCCOMB_X75_Y1_N22
cycloneii_lcell_comb \REGISTER[5]~feeder (
// Equation(s):
// \REGISTER[5]~feeder_combout  = REGISTER[4]

	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(REGISTER[4]),
	.cin(gnd),
	.combout(\REGISTER[5]~feeder_combout ),
	.cout());
// synopsys translate_off
defparam \REGISTER[5]~feeder .lut_mask = 16'hFF00;
defparam \REGISTER[5]~feeder .sum_lutc_input = "datac";
// synopsys translate_on

// atom is at LCFF_X75_Y1_N23
cycloneii_lcell_ff \REGISTER[5] (
	.clk(\CLK~clkctrl_outclk ),
	.datain(\REGISTER[5]~feeder_combout ),
	.sdata(gnd),
	.aclr(\RST~clkctrl_outclk ),
	.sclr(gnd),
	.sload(gnd),
	.ena(\OUTEN~combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(REGISTER[5]));

// atom is at LCCOMB_X75_Y1_N8
cycloneii_lcell_comb \REGISTER[6]~feeder (
// Equation(s):
// \REGISTER[6]~feeder_combout  = REGISTER[5]

	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(REGISTER[5]),
	.cin(gnd),
	.combout(\REGISTER[6]~feeder_combout ),
	.cout());
// synopsys translate_off
defparam \REGISTER[6]~feeder .lut_mask = 16'hFF00;
defparam \REGISTER[6]~feeder .sum_lutc_input = "datac";
// synopsys translate_on

// atom is at LCFF_X75_Y1_N9
cycloneii_lcell_ff \REGISTER[6] (
	.clk(\CLK~clkctrl_outclk ),
	.datain(\REGISTER[6]~feeder_combout ),
	.sdata(gnd),
	.aclr(\RST~clkctrl_outclk ),
	.sclr(gnd),
	.sload(gnd),
	.ena(\OUTEN~combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(REGISTER[6]));

// atom is at LCFF_X75_Y1_N3
cycloneii_lcell_ff \REGISTER[7] (
	.clk(\CLK~clkctrl_outclk ),
	.datain(gnd),
	.sdata(REGISTER[6]),
	.aclr(\RST~clkctrl_outclk ),
	.sclr(gnd),
	.sload(vcc),
	.ena(\OUTEN~combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(REGISTER[7]));

// atom is at LCCOMB_X75_Y1_N26
cycloneii_lcell_comb \REGISTER[8]~feeder (
// Equation(s):
// \REGISTER[8]~feeder_combout  = REGISTER[7]

	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(REGISTER[7]),
	.cin(gnd),
	.combout(\REGISTER[8]~feeder_combout ),
	.cout());
// synopsys translate_off
defparam \REGISTER[8]~feeder .lut_mask = 16'hFF00;
defparam \REGISTER[8]~feeder .sum_lutc_input = "datac";