test_gate.fdo

来自「用VHDL编写的串口异步通信的例子」· FDO 代码 · 共 14 行

## NOTE:  Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Mon Mar 26 20:11:34 China Standard Time 2007
##
vlib work
vlog  k.v
vlog  "D:/Program Files/Xilinx ISE 7.1i/verilog/src/glbl.v"
vsim -t 1ps  -L cpld_ver -L uni9000_ver  -lib work TEST_gate glbl
do {TEST_gate.udo}
view wave
add wave *
view structure
view signals
run 1000ns