kkk.vhw

用VHDL编写的串口异步通信的例子

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 7.1.04i
--  \   \         Application : ISE Foundation
--  /   /         Filename : kkk.vhw
-- /___/   /\     Timestamp : Tue Mar 27 11:45:15 2007
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: 
--Design Name: kkk
--Device: Xilinx
--

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY kkk IS
END kkk;

ARCHITECTURE testbench_arch OF kkk IS
    FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";

    COMPONENT yibutongxin
        PORT (
            sin : In std_logic;
            rxclk : In std_logic;
            txclk : In std_logic;
            tran : In std_logic;
            ldsr : Buffer std_logic;
            ldrb : Buffer std_logic;
            fe : Out std_logic;
            d : Out std_logic_vector (7 DownTo 0);
            rxbuff : Buffer std_logic_vector (7 DownTo 0);
            sclk : Buffer std_logic
        );
    END COMPONENT;

    SIGNAL sin : std_logic := '0';
    SIGNAL rxclk : std_logic := '0';
    SIGNAL txclk : std_logic := '0';
    SIGNAL tran : std_logic := '0';
    SIGNAL ldsr : std_logic := '0';
    SIGNAL ldrb : std_logic := '0';
    SIGNAL fe : std_logic := '0';
    SIGNAL d : std_logic_vector (7 DownTo 0) := "00000000";
    SIGNAL rxbuff : std_logic_vector (7 DownTo 0) := "00000000";
    SIGNAL sclk : std_logic := '0';

    SHARED VARIABLE TX_ERROR : INTEGER := 0;
    SHARED VARIABLE TX_OUT : LINE;

    constant PERIOD : time := 200 ns;
    constant DUTY_CYCLE : real := 0.5;
    constant OFFSET : time := 0 ns;

    BEGIN
        UUT : yibutongxin
        PORT MAP (
            sin => sin,
            rxclk => rxclk,
            txclk => txclk,
            tran => tran,
            ldsr => ldsr,
            ldrb => ldrb,
            fe => fe,
            d => d,
            rxbuff => rxbuff,
            sclk => sclk
        );

        PROCESS    -- clock process for rxclk
        BEGIN
            WAIT for OFFSET;
            CLOCK_LOOP : LOOP
                rxclk <= '0';
                WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE));
                rxclk <= '1';
                WAIT FOR (PERIOD * DUTY_CYCLE);
            END LOOP CLOCK_LOOP;
        END PROCESS;

        PROCESS
            PROCEDURE CHECK_d(
                next_d : std_logic_vector (7 DownTo 0);
                TX_TIME : INTEGER
            ) IS
                VARIABLE TX_STR : String(1 to 4096);
                VARIABLE TX_LOC : LINE;
                BEGIN
                IF (d /= next_d) THEN
                    STD.TEXTIO.write(TX_LOC, string'("Error at time="));
                    STD.TEXTIO.write(TX_LOC, TX_TIME);
                    STD.TEXTIO.write(TX_LOC, string'("ns d="));
                    IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, d);
                    STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
                    IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_d);
                    STD.TEXTIO.write(TX_LOC, string'(" "));
                    TX_STR(TX_LOC.all'range) := TX_LOC.all;
                    STD.TEXTIO.writeline(RESULTS, TX_LOC);
                    STD.TEXTIO.Deallocate(TX_LOC);
                    ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
                    TX_ERROR := TX_ERROR + 1;
                END IF;
            END;
            PROCEDURE CHECK_fe(
                next_fe : std_logic;
                TX_TIME : INTEGER
            ) IS
                VARIABLE TX_STR : String(1 to 4096);
                VARIABLE TX_LOC : LINE;
                BEGIN
                IF (fe /= next_fe) THEN
                    STD.TEXTIO.write(TX_LOC, string'("Error at time="));
                    STD.TEXTIO.write(TX_LOC, TX_TIME);
                    STD.TEXTIO.write(TX_LOC, string'("ns fe="));
                    IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, fe);
                    STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
                    IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_fe);
                    STD.TEXTIO.write(TX_LOC, string'(" "));
                    TX_STR(TX_LOC.all'range) := TX_LOC.all;
                    STD.TEXTIO.writeline(RESULTS, TX_LOC);
                    STD.TEXTIO.Deallocate(TX_LOC);
                    ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
                    TX_ERROR := TX_ERROR + 1;
                END IF;
            END;
            BEGIN
                WAIT FOR 1200 ns;

                IF (TX_ERROR = 0) THEN
                    STD.TEXTIO.write(TX_OUT, string'("No errors or warnings"));
                    STD.TEXTIO.writeline(RESULTS, TX_OUT);
                    ASSERT (FALSE) REPORT
                      "Simulation successful (not a failure).  No problems detected."
                      SEVERITY FAILURE;
                ELSE
                    STD.TEXTIO.write(TX_OUT, TX_ERROR);
                    STD.TEXTIO.write(TX_OUT,
                        string'(" errors found in simulation"));
                    STD.TEXTIO.writeline(RESULTS, TX_OUT);
                    ASSERT (FALSE) REPORT "Errors found during simulation"
                         SEVERITY FAILURE;
                END IF;
            END PROCESS;

    END testbench_arch;