jishu0.fit.qmsg

Verilog 实现9999计数

{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Info: Started processing fast register assignments" {  } {  } 0 0 "Started processing fast register assignments" 0 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Info: Finished processing fast register assignments" {  } {  } 0 0 "Finished processing fast register assignments" 0 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Extra Info: Finished moving registers into LUTs: elapsed time is 00:00:00" {  } {  } 1 0 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "9.349 ns register pin " "Info: Estimated most critical path is register to pin delay of 9.349 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns jishu1:inst2\|qh2\[2\] 1 REG LAB_X4_Y1 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X4_Y1; Fanout = 5; REG Node = 'jishu1:inst2\|qh2\[2\]'" {  } { { "e:/eda/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/win/TimingClosureFloorplan.fld" "" "" { jishu1:inst2|qh2[2] } "NODE_NAME" } } { "jishu1.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/jishu1.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.845 ns) + CELL(0.511 ns) 1.356 ns mux:inst5\|Selector1~239 2 COMB LAB_X4_Y1 1 " "Info: 2: + IC(0.845 ns) + CELL(0.511 ns) = 1.356 ns; Loc. = LAB_X4_Y1; Fanout = 1; COMB Node = 'mux:inst5\|Selector1~239'" {  } { { "e:/eda/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/win/TimingClosureFloorplan.fld" "" "1.356 ns" { jishu1:inst2|qh2[2] mux:inst5|Selector1~239 } "NODE_NAME" } } { "mux.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/mux.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.980 ns) + CELL(0.200 ns) 2.536 ns mux:inst5\|Selector1~240 3 COMB LAB_X4_Y1 8 " "Info: 3: + IC(0.980 ns) + CELL(0.200 ns) = 2.536 ns; Loc. = LAB_X4_Y1; Fanout = 8; COMB Node = 'mux:inst5\|Selector1~240'" {  } { { "e:/eda/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/win/TimingClosureFloorplan.fld" "" "1.180 ns" { mux:inst5|Selector1~239 mux:inst5|Selector1~240 } "NODE_NAME" } } { "mux.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/mux.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.726 ns) + CELL(0.511 ns) 4.773 ns yima:inst4\|WideOr6~23 4 COMB LAB_X6_Y1 1 " "Info: 4: + IC(1.726 ns) + CELL(0.511 ns) = 4.773 ns; Loc. = LAB_X6_Y1; Fanout = 1; COMB Node = 'yima:inst4\|WideOr6~23'" {  } { { "e:/eda/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/win/TimingClosureFloorplan.fld" "" "2.237 ns" { mux:inst5|Selector1~240 yima:inst4|WideOr6~23 } "NODE_NAME" } } { "yima.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/yima.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.254 ns) + CELL(2.322 ns) 9.349 ns q\[1\] 5 PIN PIN_16 0 " "Info: 5: + IC(2.254 ns) + CELL(2.322 ns) = 9.349 ns; Loc. = PIN_16; Fanout = 0; PIN Node = 'q\[1\]'" {  } { { "e:/eda/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/win/TimingClosureFloorplan.fld" "" "4.576 ns" { yima:inst4|WideOr6~23 q[1] } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "F:/寒假/写好的EDA程序/新建文件夹/9999/Block1.bdf" { { 120 520 696 136 "q\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.544 ns ( 37.91 % ) " "Info: Total cell delay = 3.544 ns ( 37.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.805 ns ( 62.09 % ) " "Info: Total interconnect delay = 5.805 ns ( 62.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/eda/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/win/TimingClosureFloorplan.fld" "" "9.349 ns" { jishu1:inst2|qh2[2] mux:inst5|Selector1~239 mux:inst5|Selector1~240 yima:inst4|WideOr6~23 q[1] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "10 10 " "Info: Average interconnect usage is 10% of the available device resources. Peak interconnect usage is 10%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x0_y0 x8_y5 " "Info: The peak interconnect region extends from location x0_y0 to location x8_y5" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "1 " "Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "d_out\[1\] VCC " "Info: Pin d_out\[1\] has VCC driving its datain port" {  } { { "Block1.bdf" "" { Schematic "F:/寒假/写好的EDA程序/新建文件夹/9999/Block1.bdf" { { -280 352 528 -264 "d_out\[4..0\]" "" } } } } { "e:/eda/win/Assignment Editor.qase" "" { Assignment "e:/eda/win/Assignment Editor.qase" 1 { { 0 "d_out\[1\]" } } } } { "e:/eda/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/win/TimingClosureFloorplan.fld" "" "" { d_out[1] } "NODE_NAME" } } { "e:/eda/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/win/TimingClosureFloorplan.fld" "" "" { d_out[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 24 08:57:57 2008 " "Info: Processing ended: Thu Jan 24 08:57:57 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Info: Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/寒假/写好的EDA程序/新建文件夹/9999/jishu0.fit.smsg " "Info: Generated suppressed messages file F:/寒假/写好的EDA程序/新建文件夹/9999/jishu0.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}