jishu0.tan.qmsg

Verilog 实现9999计数

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "fen1hz:inst7\|f1hz " "Info: Detected ripple clock \"fen1hz:inst7\|f1hz\" as buffer" {  } { { "fen1hz.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/fen1hz.v" 3 -1 0 } } { "e:/eda/win/Assignment Editor.qase" "" { Assignment "e:/eda/win/Assignment Editor.qase" 1 { { 0 "fen1hz:inst7\|f1hz" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "jishu1:inst2\|cy1 " "Info: Detected ripple clock \"jishu1:inst2\|cy1\" as buffer" {  } { { "jishu1.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/jishu1.v" 5 -1 0 } } { "e:/eda/win/Assignment Editor.qase" "" { Assignment "e:/eda/win/Assignment Editor.qase" 1 { { 0 "jishu1:inst2\|cy1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fen1k:inst\|f1k " "Info: Detected ripple clock \"fen1k:inst\|f1k\" as buffer" {  } { { "fen1k.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/fen1k.v" 3 -1 0 } } { "e:/eda/win/Assignment Editor.qase" "" { Assignment "e:/eda/win/Assignment Editor.qase" 1 { { 0 "fen1k:inst\|f1k" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_in0 register fen1hz:inst7\|cn\[19\] register fen1hz:inst7\|cn\[5\] 93.41 MHz 10.705 ns Internal " "Info: Clock \"clk_in0\" has Internal fmax of 93.41 MHz between source register \"fen1hz:inst7\|cn\[19\]\" and destination register \"fen1hz:inst7\|cn\[5\]\" (period= 10.705 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.996 ns + Longest register register " "Info: + Longest register to register delay is 9.996 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fen1hz:inst7\|cn\[19\] 1 REG LC_X5_Y2_N3 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y2_N3; Fanout = 4; REG Node = 'fen1hz:inst7\|cn\[19\]'" {  } { { "e:/eda/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/win/TimingClosureFloorplan.fld" "" "" { fen1hz:inst7|cn[19] } "NODE_NAME" } } { "fen1hz.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/fen1hz.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.452 ns) + CELL(0.914 ns) 3.366 ns fen1hz:inst7\|LessThan0~504 2 COMB LC_X2_Y3_N6 1 " "Info: 2: + IC(2.452 ns) + CELL(0.914 ns) = 3.366 ns; Loc. = LC_X2_Y3_N6; Fanout = 1; COMB Node = 'fen1hz:inst7\|LessThan0~504'" {  } { { "e:/eda/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/win/TimingClosureFloorplan.fld" "" "3.366 ns" { fen1hz:inst7|cn[19] fen1hz:inst7|LessThan0~504 } "NODE_NAME" } } { "fen1hz.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/fen1hz.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.292 ns) + CELL(0.200 ns) 5.858 ns fen1hz:inst7\|LessThan0~506 3 COMB LC_X6_Y2_N8 2 " "Info: 3: + IC(2.292 ns) + CELL(0.200 ns) = 5.858 ns; Loc. = LC_X6_Y2_N8; Fanout = 2; COMB Node = 'fen1hz:inst7\|LessThan0~506'" {  } { { "e:/eda/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/win/TimingClosureFloorplan.fld" "" "2.492 ns" { fen1hz:inst7|LessThan0~504 fen1hz:inst7|LessThan0~506 } "NODE_NAME" } } { "fen1hz.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/fen1hz.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 6.363 ns fen1hz:inst7\|LessThan0~509 4 COMB LC_X6_Y2_N9 32 " "Info: 4: + IC(0.305 ns) + CELL(0.200 ns) = 6.363 ns; Loc. = LC_X6_Y2_N9; Fanout = 32; COMB Node = 'fen1hz:inst7\|LessThan0~509'" {  } { { "e:/eda/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/win/TimingClosureFloorplan.fld" "" "0.505 ns" { fen1hz:inst7|LessThan0~506 fen1hz:inst7|LessThan0~509 } "NODE_NAME" } } { "fen1hz.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/fen1hz.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.873 ns) + CELL(1.760 ns) 9.996 ns fen1hz:inst7\|cn\[5\] 5 REG LC_X3_Y2_N9 3 " "Info: 5: + IC(1.873 ns) + CELL(1.760 ns) = 9.996 ns; Loc. = LC_X3_Y2_N9; Fanout = 3; REG Node = 'fen1hz:inst7\|cn\[5\]'" {  } { { "e:/eda/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/win/TimingClosureFloorplan.fld" "" "3.633 ns" { fen1hz:inst7|LessThan0~509 fen1hz:inst7|cn[5] } "NODE_NAME" } } { "fen1hz.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/fen1hz.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.074 ns ( 30.75 % ) " "Info: Total cell delay = 3.074 ns ( 30.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.922 ns ( 69.25 % ) " "Info: Total interconnect delay = 6.922 ns ( 69.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/eda/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/win/TimingClosureFloorplan.fld" "" "9.996 ns" { fen1hz:inst7|cn[19] fen1hz:inst7|LessThan0~504 fen1hz:inst7|LessThan0~506 fen1hz:inst7|LessThan0~509 fen1hz:inst7|cn[5] } "NODE_NAME" } } { "e:/eda/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/eda/win/Technology_Viewer.qrui" "9.996 ns" { fen1hz:inst7|cn[19] fen1hz:inst7|LessThan0~504 fen1hz:inst7|LessThan0~506 fen1hz:inst7|LessThan0~509 fen1hz:inst7|cn[5] } { 0.000ns 2.452ns 2.292ns 0.305ns 1.873ns } { 0.000ns 0.914ns 0.200ns 0.200ns 1.760ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in0 destination 9.330 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_in0\" to destination register is 9.330 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk_in0 1 CLK PIN_12 33 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 33; CLK Node = 'clk_in0'" {  } { { "e:/eda/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/win/TimingClosureFloorplan.fld" "" "" { clk_in0 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "F:/寒假/写好的EDA程序/新建文件夹/9999/Block1.bdf" { { -104 -96 72 -88 "clk_in0" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns fen1k:inst\|f1k 2 REG LC_X6_Y4_N9 39 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X6_Y4_N9; Fanout = 39; REG Node = 'fen1k:inst\|f1k'" {  } { { "e:/eda/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/win/TimingClosureFloorplan.fld" "" "2.561 ns" { clk_in0 fen1k:inst|f1k } "NODE_NAME" } } { "fen1k.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/fen1k.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.688 ns) + CELL(0.918 ns) 9.330 ns fen1hz:inst7\|cn\[5\] 3 REG LC_X3_Y2_N9 3 " "Info: 3: + IC(4.688 ns) + CELL(0.918 ns) = 9.330 ns; Loc. = LC_X3_Y2_N9; Fanout = 3; REG Node = 'fen1hz:inst7\|cn\[5\]'" {  } { { "e:/eda/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/win/TimingClosureFloorplan.fld" "" "5.606 ns" { fen1k:inst|f1k fen1hz:inst7|cn[5] } "NODE_NAME" } } { "fen1hz.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/fen1hz.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 36.17 % ) " "Info: Total cell delay = 3.375 ns ( 36.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.955 ns ( 63.83 % ) " "Info: Total interconnect delay = 5.955 ns ( 63.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/eda/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/win/TimingClosureFloorplan.fld" "" "9.330 ns" { clk_in0 fen1k:inst|f1k fen1hz:inst7|cn[5] } "NODE_NAME" } } { "e:/eda/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/eda/win/Technology_Viewer.qrui" "9.330 ns" { clk_in0 clk_in0~combout fen1k:inst|f1k fen1hz:inst7|cn[5] } { 0.000ns 0.000ns 1.267ns 4.688ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in0 source 9.330 ns - Longest register " "Info: - Longest clock path from clock \"clk_in0\" to source register is 9.330 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk_in0 1 CLK PIN_12 33 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 33; CLK Node = 'clk_in0'" {  } { { "e:/eda/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/win/TimingClosureFloorplan.fld" "" "" { clk_in0 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "F:/寒假/写好的EDA程序/新建文件夹/9999/Block1.bdf" { { -104 -96 72 -88 "clk_in0" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns fen1k:inst\|f1k 2 REG LC_X6_Y4_N9 39 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X6_Y4_N9; Fanout = 39; REG Node = 'fen1k:inst\|f1k'" {  } { { "e:/eda/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/win/TimingClosureFloorplan.fld" "" "2.561 ns" { clk_in0 fen1k:inst|f1k } "NODE_NAME" } } { "fen1k.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/fen1k.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.688 ns) + CELL(0.918 ns) 9.330 ns fen1hz:inst7\|cn\[19\] 3 REG LC_X5_Y2_N3 4 " "Info: 3: + IC(4.688 ns) + CELL(0.918 ns) = 9.330 ns; Loc. = LC_X5_Y2_N3; Fanout = 4; REG Node = 'fen1hz:inst7\|cn\[19\]'" {  } { { "e:/eda/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/win/TimingClosureFloorplan.fld" "" "5.606 ns" { fen1k:inst|f1k fen1hz:inst7|cn[19] } "NODE_NAME" } } { "fen1hz.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/fen1hz.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 36.17 % ) " "Info: Total cell delay = 3.375 ns ( 36.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.955 ns ( 63.83 % ) " "Info: Total interconnect delay = 5.955 ns ( 63.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/eda/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/win/TimingClosureFloorplan.fld" "" "9.330 ns" { clk_in0 fen1k:inst|f1k fen1hz:inst7|cn[19] } "NODE_NAME" } } { "e:/eda/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/eda/win/Technology_Viewer.qrui" "9.330 ns" { clk_in0 clk_in0~combout fen1k:inst|f1k fen1hz:inst7|cn[19] } { 0.000ns 0.000ns 1.267ns 4.688ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/eda/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/win/TimingClosureFloorplan.fld" "" "9.330 ns" { clk_in0 fen1k:inst|f1k fen1hz:inst7|cn[5] } "NODE_NAME" } } { "e:/eda/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/eda/win/Technology_Viewer.qrui" "9.330 ns" { clk_in0 clk_in0~combout fen1k:inst|f1k fen1hz:inst7|cn[5] } { 0.000ns 0.000ns 1.267ns 4.688ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } } { "e:/eda/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/win/TimingClosureFloorplan.fld" "" "9.330 ns" { clk_in0 fen1k:inst|f1k fen1hz:inst7|cn[19] } "NODE_NAME" } } { "e:/eda/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/eda/win/Technology_Viewer.qrui" "9.330 ns" { clk_in0 clk_in0~combout fen1k:inst|f1k fen1hz:inst7|cn[19] } { 0.000ns 0.000ns 1.267ns 4.688ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "fen1hz.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/fen1hz.v" 18 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "fen1hz.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/fen1hz.v" 18 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/eda/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/win/TimingClosureFloorplan.fld" "" "9.996 ns" { fen1hz:inst7|cn[19] fen1hz:inst7|LessThan0~504 fen1hz:inst7|LessThan0~506 fen1hz:inst7|LessThan0~509 fen1hz:inst7|cn[5] } "NODE_NAME" } } { "e:/eda/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/eda/win/Technology_Viewer.qrui" "9.996 ns" { fen1hz:inst7|cn[19] fen1hz:inst7|LessThan0~504 fen1hz:inst7|LessThan0~506 fen1hz:inst7|LessThan0~509 fen1hz:inst7|cn[5] } { 0.000ns 2.452ns 2.292ns 0.305ns 1.873ns } { 0.000ns 0.914ns 0.200ns 0.200ns 1.760ns } } } { "e:/eda/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/win/TimingClosureFloorplan.fld" "" "9.330 ns" { clk_in0 fen1k:inst|f1k fen1hz:inst7|cn[5] } "NODE_NAME" } } { "e:/eda/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/eda/win/Technology_Viewer.qrui" "9.330 ns" { clk_in0 clk_in0~combout fen1k:inst|f1k fen1hz:inst7|cn[5] } { 0.000ns 0.000ns 1.267ns 4.688ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } } { "e:/eda/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/win/TimingClosureFloorplan.fld" "" "9.330 ns" { clk_in0 fen1k:inst|f1k fen1hz:inst7|cn[19] } "NODE_NAME" } } { "e:/eda/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/eda/win/Technology_Viewer.qrui" "9.330 ns" { clk_in0 clk_in0~combout fen1k:inst|f1k fen1hz:inst7|cn[19] } { 0.000ns 0.000ns 1.267ns 4.688ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk_in0 q\[0\] jishu1:inst2\|qh3\[1\] 29.253 ns register " "Info: tco from clock \"clk_in0\" to destination pin \"q\[0\]\" through register \"jishu1:inst2\|qh3\[1\]\" is 29.253 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in0 source 19.486 ns + Longest register " "Info: + Longest clock path from clock \"clk_in0\" to source register is 19.486 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk_in0 1 CLK PIN_12 33 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 33; CLK Node = 'clk_in0'" {  } { { "e:/eda/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/win/TimingClosureFloorplan.fld" "" "" { clk_in0 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "F:/寒假/写好的EDA程序/新建文件夹/9999/Block1.bdf" { { -104 -96 72 -88 "clk_in0" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns fen1k:inst\|f1k 2 REG LC_X6_Y4_N9 39 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X6_Y4_N9; Fanout = 39; REG Node = 'fen1k:inst\|f1k'" {  } { { "e:/eda/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/win/TimingClosureFloorplan.fld" "" "2.561 ns" { clk_in0 fen1k:inst|f1k } "NODE_NAME" } } { "fen1k.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/fen1k.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.688 ns) + CELL(1.294 ns) 9.706 ns fen1hz:inst7\|f1hz 3 REG LC_X6_Y2_N9 9 " "Info: 3: + IC(4.688 ns) + CELL(1.294 ns) = 9.706 ns; Loc. = LC_X6_Y2_N9; Fanout = 9; REG Node = 'fen1hz:inst7\|f1hz'" {  } { { "e:/eda/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/win/TimingClosureFloorplan.fld" "" "5.982 ns" { fen1k:inst|f1k fen1hz:inst7|f1hz } "NODE_NAME" } } { "fen1hz.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/fen1hz.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.001 ns) + CELL(1.294 ns) 15.001 ns jishu1:inst2\|cy1 4 REG LC_X2_Y1_N1 9 " "Info: 4: + IC(4.001 ns) + CELL(1.294 ns) = 15.001 ns; Loc. = LC_X2_Y1_N1; Fanout = 9; REG Node = 'jishu1:inst2\|cy1'" {  } { { "e:/eda/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/win/TimingClosureFloorplan.fld" "" "5.295 ns" { fen1hz:inst7|f1hz jishu1:inst2|cy1 } "NODE_NAME" } } { "jishu1.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/jishu1.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.567 ns) + CELL(0.918 ns) 19.486 ns jishu1:inst2\|qh3\[1\] 5 REG LC_X4_Y3_N2 4 " "Info: 5: + IC(3.567 ns) + CELL(0.918 ns) = 19.486 ns; Loc. = LC_X4_Y3_N2; Fanout = 4; REG Node = 'jishu1:inst2\|qh3\[1\]'" {  } { { "e:/eda/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/win/TimingClosureFloorplan.fld" "" "4.485 ns" { jishu1:inst2|cy1 jishu1:inst2|qh3[1] } "NODE_NAME" } } { "jishu1.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/jishu1.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.963 ns ( 30.60 % ) " "Info: Total cell delay = 5.963 ns ( 30.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "13.523 ns ( 69.40 % ) " "Info: Total interconnect delay = 13.523 ns ( 69.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/eda/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/win/TimingClosureFloorplan.fld" "" "19.486 ns" { clk_in0 fen1k:inst|f1k fen1hz:inst7|f1hz jishu1:inst2|cy1 jishu1:inst2|qh3[1] } "NODE_NAME" } } { "e:/eda/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/eda/win/Technology_Viewer.qrui" "19.486 ns" { clk_in0 clk_in0~combout fen1k:inst|f1k fen1hz:inst7|f1hz jishu1:inst2|cy1 jishu1:inst2|qh3[1] } { 0.000ns 0.000ns 1.267ns 4.688ns 4.001ns 3.567ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "jishu1.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/jishu1.v" 25 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.391 ns + Longest register pin " "Info: + Longest register to pin delay is 9.391 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns jishu1:inst2\|qh3\[1\] 1 REG LC_X4_Y3_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y3_N2; Fanout = 4; REG Node = 'jishu1:inst2\|qh3\[1\]'" {  } { { "e:/eda/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/win/TimingClosureFloorplan.fld" "" "" { jishu1:inst2|qh3[1] } "NODE_NAME" } } { "jishu1.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/jishu1.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.036 ns) + CELL(0.511 ns) 2.547 ns mux:inst5\|Selector2~206 2 COMB LC_X4_Y1_N8 8 " "Info: 2: + IC(2.036 ns) + CELL(0.511 ns) = 2.547 ns; Loc. = LC_X4_Y1_N8; Fanout = 8; COMB Node = 'mux:inst5\|Selector2~206'" {  } { { "e:/eda/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/win/TimingClosureFloorplan.fld" "" "2.547 ns" { jishu1:inst2|qh3[1] mux:inst5|Selector2~206 } "NODE_NAME" } } { "mux.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/mux.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.716 ns) + CELL(0.200 ns) 4.463 ns yima:inst4\|WideOr7~23 3 COMB LC_X6_Y1_N1 1 " "Info: 3: + IC(1.716 ns) + CELL(0.200 ns) = 4.463 ns; Loc. = LC_X6_Y1_N1; Fanout = 1; COMB Node = 'yima:inst4\|WideOr7~23'" {  } { { "e:/eda/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/win/TimingClosureFloorplan.fld" "" "1.916 ns" { mux:inst5|Selector2~206 yima:inst4|WideOr7~23 } "NODE_NAME" } } { "yima.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/yima.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.606 ns) + CELL(2.322 ns) 9.391 ns q\[0\] 4 PIN PIN_15 0 " "Info: 4: + IC(2.606 ns) + CELL(2.322 ns) = 9.391 ns; Loc. = PIN_15; Fanout = 0; PIN Node = 'q\[0\]'" {  } { { "e:/eda/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/win/TimingClosureFloorplan.fld" "" "4.928 ns" { yima:inst4|WideOr7~23 q[0] } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "F:/寒假/写好的EDA程序/新建文件夹/9999/Block1.bdf" { { 120 520 696 136 "q\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.033 ns ( 32.30 % ) " "Info: Total cell delay = 3.033 ns ( 32.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.358 ns ( 67.70 % ) " "Info: Total interconnect delay = 6.358 ns ( 67.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/eda/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/win/TimingClosureFloorplan.fld" "" "9.391 ns" { jishu1:inst2|qh3[1] mux:inst5|Selector2~206 yima:inst4|WideOr7~23 q[0] } "NODE_NAME" } } { "e:/eda/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/eda/win/Technology_Viewer.qrui" "9.391 ns" { jishu1:inst2|qh3[1] mux:inst5|Selector2~206 yima:inst4|WideOr7~23 q[0] } { 0.000ns 2.036ns 1.716ns 2.606ns } { 0.000ns 0.511ns 0.200ns 2.322ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/eda/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/win/TimingClosureFloorplan.fld" "" "19.486 ns" { clk_in0 fen1k:inst|f1k fen1hz:inst7|f1hz jishu1:inst2|cy1 jishu1:inst2|qh3[1] } "NODE_NAME" } } { "e:/eda/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/eda/win/Technology_Viewer.qrui" "19.486 ns" { clk_in0 clk_in0~combout fen1k:inst|f1k fen1hz:inst7|f1hz jishu1:inst2|cy1 jishu1:inst2|qh3[1] } { 0.000ns 0.000ns 1.267ns 4.688ns 4.001ns 3.567ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 0.918ns } } } { "e:/eda/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/eda/win/TimingClosureFloorplan.fld" "" "9.391 ns" { jishu1:inst2|qh3[1] mux:inst5|Selector2~206 yima:inst4|WideOr7~23 q[0] } "NODE_NAME" } } { "e:/eda/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/eda/win/Technology_Viewer.qrui" "9.391 ns" { jishu1:inst2|qh3[1] mux:inst5|Selector2~206 yima:inst4|WideOr7~23 q[0] } { 0.000ns 2.036ns 1.716ns 2.606ns } { 0.000ns 0.511ns 0.200ns 2.322ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 24 08:58:27 2008 " "Info: Processing ended: Thu Jan 24 08:58:27 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}