jishu0.map.qmsg

Verilog 实现9999计数

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "yima yima:inst4 " "Info: Elaborating entity \"yima\" for hierarchy \"yima:inst4\"" {  } { { "Block1.bdf" "inst4" { Schematic "F:/寒假/写好的EDA程序/新建文件夹/9999/Block1.bdf" { { -32 536 664 64 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux mux:inst5 " "Info: Elaborating entity \"mux\" for hierarchy \"mux:inst5\"" {  } { { "Block1.bdf" "inst5" { Schematic "F:/寒假/写好的EDA程序/新建文件夹/9999/Block1.bdf" { { -240 496 664 -80 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "jishu1 jishu1:inst2 " "Info: Elaborating entity \"jishu1\" for hierarchy \"jishu1:inst2\"" {  } { { "Block1.bdf" "inst2" { Schematic "F:/寒假/写好的EDA程序/新建文件夹/9999/Block1.bdf" { { -224 320 448 -96 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "cy3 jishu1.v(5) " "Warning (10036): Verilog HDL or VHDL warning at jishu1.v(5): object \"cy3\" assigned a value but never read" {  } { { "jishu1.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/jishu1.v" 5 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 jishu1.v(16) " "Warning (10230): Verilog HDL assignment warning at jishu1.v(16): truncated value with size 32 to match size of target (4)" {  } { { "jishu1.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/jishu1.v" 16 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 jishu1.v(20) " "Warning (10230): Verilog HDL assignment warning at jishu1.v(20): truncated value with size 32 to match size of target (4)" {  } { { "jishu1.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/jishu1.v" 20 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 jishu1.v(34) " "Warning (10230): Verilog HDL assignment warning at jishu1.v(34): truncated value with size 32 to match size of target (4)" {  } { { "jishu1.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/jishu1.v" 34 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 jishu1.v(38) " "Warning (10230): Verilog HDL assignment warning at jishu1.v(38): truncated value with size 32 to match size of target (4)" {  } { { "jishu1.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/jishu1.v" 38 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 jishu1.v(49) " "Warning (10230): Verilog HDL assignment warning at jishu1.v(49): truncated value with size 32 to match size of target (4)" {  } { { "jishu1.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/jishu1.v" 49 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fen1hz fen1hz:inst7 " "Info: Elaborating entity \"fen1hz\" for hierarchy \"fen1hz:inst7\"" {  } { { "Block1.bdf" "inst7" { Schematic "F:/寒假/写好的EDA程序/新建文件夹/9999/Block1.bdf" { { -128 200 296 -32 "inst7" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "dispselect:inst1\|wei_out\[1\]~reg0 High " "Info: Power-up level of register \"dispselect:inst1\|wei_out\[1\]~reg0\" is not specified -- using power-up level of High to minimize register" {  } { { "dispselect.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/dispselect.v" 20 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "dispselect:inst1\|wei_out\[1\]~reg0 data_in VCC " "Warning: Reduced register \"dispselect:inst1\|wei_out\[1\]~reg0\" with stuck data_in port to stuck value VCC" {  } { { "dispselect.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/dispselect.v" 20 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR_HDR" "" "Warning: Converted TRI buffer or tri-state bus to logic, or removed OPNDRN" { { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "mux:inst5\|out\[3\] " "Warning: Converting TRI node \"mux:inst5\|out\[3\]\" that feeds logic to a wire" {  } { { "mux.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/mux.v" 4 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "mux:inst5\|out\[2\] " "Warning: Converting TRI node \"mux:inst5\|out\[2\]\" that feeds logic to a wire" {  } { { "mux.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/mux.v" 4 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "mux:inst5\|out\[1\] " "Warning: Converting TRI node \"mux:inst5\|out\[1\]\" that feeds logic to a wire" {  } { { "mux.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/mux.v" 4 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "mux:inst5\|out\[0\] " "Warning: Converting TRI node \"mux:inst5\|out\[0\]\" that feeds logic to a wire" {  } { { "mux.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/mux.v" 4 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0}  } {  } 0 0 "Converted TRI buffer or tri-state bus to logic, or removed OPNDRN" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "dispselect:inst1\|always0~5 dispselect:inst1\|always0~0 " "Info: Duplicate register \"dispselect:inst1\|always0~5\" merged to single register \"dispselect:inst1\|always0~0\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "dispselect:inst1\|always0~1 dispselect:inst1\|always0~0 " "Info: Duplicate register \"dispselect:inst1\|always0~1\" merged to single register \"dispselect:inst1\|always0~0\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "dispselect:inst1\|always0~3 dispselect:inst1\|always0~0 " "Info: Duplicate register \"dispselect:inst1\|always0~3\" merged to single register \"dispselect:inst1\|always0~0\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "dispselect:inst1\|always0~7 dispselect:inst1\|always0~0 " "Info: Duplicate register \"dispselect:inst1\|always0~7\" merged to single register \"dispselect:inst1\|always0~0\"" {  } {  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "dispselect:inst1\|wei\[2\] data_in GND " "Warning: Reduced register \"dispselect:inst1\|wei\[2\]\" with stuck data_in port to stuck value GND" {  } { { "dispselect.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/dispselect.v" 20 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "dispselect:inst1\|always0~0 High " "Info: Power-up level of register \"dispselect:inst1\|always0~0\" is not specified -- using power-up level of High to minimize register" {  } {  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "dispselect:inst1\|always0~0 data_in VCC " "Warning: Reduced register \"dispselect:inst1\|always0~0\" with stuck data_in port to stuck value VCC" {  } {  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "dispselect:inst1\|wei_out\[4\] " "Warning: Removed always-enabled tri-state buffer dispselect:inst1\|wei_out\[4\] feeding logic, open-drain buffer, or output pin" {  } { { "dispselect.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/dispselect.v" 20 -1 0 } }  } 0 0 "Removed always-enabled tri-state buffer %1!s! feeding logic, open-drain buffer, or output pin" 0 0}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "dispselect:inst1\|wei_out\[3\] " "Warning: Removed always-enabled tri-state buffer dispselect:inst1\|wei_out\[3\] feeding logic, open-drain buffer, or output pin" {  } { { "dispselect.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/dispselect.v" 20 -1 0 } }  } 0 0 "Removed always-enabled tri-state buffer %1!s! feeding logic, open-drain buffer, or output pin" 0 0}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "dispselect:inst1\|wei_out\[2\] " "Warning: Removed always-enabled tri-state buffer dispselect:inst1\|wei_out\[2\] feeding logic, open-drain buffer, or output pin" {  } { { "dispselect.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/dispselect.v" 20 -1 0 } }  } 0 0 "Removed always-enabled tri-state buffer %1!s! feeding logic, open-drain buffer, or output pin" 0 0}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "dispselect:inst1\|wei_out\[1\] " "Warning: Removed always-enabled tri-state buffer dispselect:inst1\|wei_out\[1\] feeding logic, open-drain buffer, or output pin" {  } { { "dispselect.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/dispselect.v" 20 -1 0 } }  } 0 0 "Removed always-enabled tri-state buffer %1!s! feeding logic, open-drain buffer, or output pin" 0 0}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "dispselect:inst1\|wei_out\[0\] " "Warning: Removed always-enabled tri-state buffer dispselect:inst1\|wei_out\[0\] feeding logic, open-drain buffer, or output pin" {  } { { "dispselect.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/dispselect.v" 20 -1 0 } }  } 0 0 "Removed always-enabled tri-state buffer %1!s! feeding logic, open-drain buffer, or output pin" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "d_out\[1\] VCC " "Warning: Pin \"d_out\[1\]\" stuck at VCC" {  } { { "Block1.bdf" "" { Schematic "F:/寒假/写好的EDA程序/新建文件夹/9999/Block1.bdf" { { -280 352 528 -264 "d_out\[4..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "145 " "Info: Implemented 145 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "13 " "Info: Implemented 13 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "131 " "Info: Implemented 131 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 29 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 29 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 24 08:57:39 2008 " "Info: Processing ended: Thu Jan 24 08:57:39 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/寒假/写好的EDA程序/新建文件夹/9999/jishu0.map.smsg " "Info: Generated suppressed messages file F:/寒假/写好的EDA程序/新建文件夹/9999/jishu0.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}