jishu0.map.qmsg

Verilog 实现9999计数

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 24 08:57:32 2008 " "Info: Processing started: Thu Jan 24 08:57:32 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off jishu0 -c jishu0 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off jishu0 -c jishu0" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "F:/寒假/写好的EDA程序/新建文件夹/9999/jishu0.v " "Warning: Can't analyze file -- file F:/寒假/写好的EDA程序/新建文件夹/9999/jishu0.v is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "yima.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file yima.v" { { "Info" "ISGN_ENTITY_NAME" "1 yima " "Info: Found entity 1: yima" {  } { { "yima.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/yima.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dis.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file dis.v" { { "Info" "ISGN_ENTITY_NAME" "1 dis " "Info: Found entity 1: dis" {  } { { "dis.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/dis.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "fegpin.v(6) " "Warning (10268): Verilog HDL information at fegpin.v(6): Always Construct contains both blocking and non-blocking assignments" {  } { { "fegpin.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/fegpin.v" 6 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fegpin.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file fegpin.v" { { "Info" "ISGN_ENTITY_NAME" "1 fen " "Info: Found entity 1: fen" {  } { { "fegpin.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/fegpin.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "F:/寒假/写好的EDA程序/新建文件夹/9999/fengpin1.v " "Warning: Can't analyze file -- file F:/寒假/写好的EDA程序/新建文件夹/9999/fengpin1.v is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Block1.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file Block1.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Block1 " "Info: Found entity 1: Block1" {  } { { "Block1.bdf" "" { Schematic "F:/寒假/写好的EDA程序/新建文件夹/9999/Block1.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WSGN_MEGAFN_REPLACE" "mux F:/寒假/写好的EDA程序/新建文件夹/9999/mux.v " "Warning: Entity \"mux\" obtained from \"F:/寒假/写好的EDA程序/新建文件夹/9999/mux.v\" instead of from Quartus II megafunction library" {  } {  } 0 0 "Entity \"%1!s!\" obtained from \"%2!s!\" instead of from Quartus II megafunction library" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mux.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file mux.v" { { "Info" "ISGN_ENTITY_NAME" "1 mux " "Info: Found entity 1: mux" {  } { { "mux.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/mux.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_XZ_EXTEND_SIGNIFICANT" "dispselect.v(18) " "Warning (10273): Verilog HDL warning at dispselect.v(18): extended using \"x\" or \"z\"" {  } { { "dispselect.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/dispselect.v" 18 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "dispselect.v(7) " "Warning (10268): Verilog HDL information at dispselect.v(7): Always Construct contains both blocking and non-blocking assignments" {  } { { "dispselect.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/dispselect.v" 7 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dispselect.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file dispselect.v" { { "Info" "ISGN_ENTITY_NAME" "1 dispselect " "Info: Found entity 1: dispselect" {  } { { "dispselect.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/dispselect.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "fen1hz.v(6) " "Warning (10268): Verilog HDL information at fen1hz.v(6): Always Construct contains both blocking and non-blocking assignments" {  } { { "fen1hz.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/fen1hz.v" 6 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fen1hz.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file fen1hz.v" { { "Info" "ISGN_ENTITY_NAME" "1 fen1hz " "Info: Found entity 1: fen1hz" {  } { { "fen1hz.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/fen1hz.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "fen1k.v(6) " "Warning (10268): Verilog HDL information at fen1k.v(6): Always Construct contains both blocking and non-blocking assignments" {  } { { "fen1k.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/fen1k.v" 6 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fen1k.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file fen1k.v" { { "Info" "ISGN_ENTITY_NAME" "1 fen1k " "Info: Found entity 1: fen1k" {  } { { "fen1k.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/fen1k.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "F:/寒假/写好的EDA程序/新建文件夹/9999/ji.v " "Warning: Can't analyze file -- file F:/寒假/写好的EDA程序/新建文件夹/9999/ji.v is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jishu1.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file jishu1.v" { { "Info" "ISGN_ENTITY_NAME" "1 jishu1 " "Info: Found entity 1: jishu1" {  } { { "jishu1.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/jishu1.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "Block1 " "Info: Elaborating entity \"Block1\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WGDFX_INCONSISTENT_BASE_NAME" "" "Warning: Found multiple base names" {  } { { "Block1.bdf" "" { Schematic "F:/寒假/写好的EDA程序/新建文件夹/9999/Block1.bdf" { { -240 496 664 -80 "inst5" "" } { -240 496 664 -80 "inst5" "" } { -240 496 664 -80 "inst5" "" } { -240 496 664 -80 "inst5" "" } { -240 496 664 -80 "inst5" "" } } } }  } 0 0 "Found multiple base names" 0 0}
{ "Warning" "WGDFX_INCONSISTENT_BASE_NAME" "" "Warning: Found multiple base names" {  } { { "Block1.bdf" "" { Schematic "F:/寒假/写好的EDA程序/新建文件夹/9999/Block1.bdf" { { -240 496 664 -80 "inst5" "" } { -240 496 664 -80 "inst5" "" } { -240 496 664 -80 "inst5" "" } { -240 496 664 -80 "inst5" "" } { -240 496 664 -80 "inst5" "" } } } }  } 0 0 "Found multiple base names" 0 0}
{ "Warning" "WGDFX_INCONSISTENT_BASE_NAME" "" "Warning: Found multiple base names" {  } { { "Block1.bdf" "" { Schematic "F:/寒假/写好的EDA程序/新建文件夹/9999/Block1.bdf" { { -240 496 664 -80 "inst5" "" } { -240 496 664 -80 "inst5" "" } { -240 496 664 -80 "inst5" "" } { -240 496 664 -80 "inst5" "" } { -240 496 664 -80 "inst5" "" } } } }  } 0 0 "Found multiple base names" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dispselect dispselect:inst1 " "Info: Elaborating entity \"dispselect\" for hierarchy \"dispselect:inst1\"" {  } { { "Block1.bdf" "inst1" { Schematic "F:/寒假/写好的EDA程序/新建文件夹/9999/Block1.bdf" { { -272 160 296 -176 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 dispselect.v(10) " "Warning (10230): Verilog HDL assignment warning at dispselect.v(10): truncated value with size 32 to match size of target (3)" {  } { { "dispselect.v" "" { Text "F:/寒假/写好的EDA程序/新建文件夹/9999/dispselect.v" 10 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fen1k fen1k:inst " "Info: Elaborating entity \"fen1k\" for hierarchy \"fen1k:inst\"" {  } { { "Block1.bdf" "inst" { Schematic "F:/寒假/写好的EDA程序/新建文件夹/9999/Block1.bdf" { { -128 80 176 -32 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}