jishu0.tan.summary

Verilog 实现9999计数

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 29.253 ns
From           : jishu1:inst2|qh3[1]
To             : q[0]
From Clock     : clk_in0
To Clock       : --
Failed Paths   : 0

Type           : Clock Setup: 'clk_in0'
Slack          : N/A
Required Time  : None
Actual Time    : 93.41 MHz ( period = 10.705 ns )
From           : fen1hz:inst7|cn[19]
To             : fen1hz:inst7|cn[1]
From Clock     : clk_in0
To Clock       : clk_in0
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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