jishu0.map.smsg

来自「Verilog 实现9999计数」· SMSG 代码 · 共 6 行

Warning (10268): Verilog HDL information at fegpin.v(6): Always Construct contains both blocking and non-blocking assignments
Warning (10273): Verilog HDL warning at dispselect.v(18): extended using "x" or "z"
Warning (10268): Verilog HDL information at dispselect.v(7): Always Construct contains both blocking and non-blocking assignments
Warning (10268): Verilog HDL information at fen1hz.v(6): Always Construct contains both blocking and non-blocking assignments
Warning (10268): Verilog HDL information at fen1k.v(6): Always Construct contains both blocking and non-blocking assignments