📄 jishu0.map.smsg

📁 Verilog 实现9999计数

💻 SMSG

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Warning (10268): Verilog HDL information at fegpin.v(6): Always Construct contains both blocking and non-blocking assignments
Warning (10273): Verilog HDL warning at dispselect.v(18): extended using "x" or "z"
Warning (10268): Verilog HDL information at dispselect.v(7): Always Construct contains both blocking and non-blocking assignments
Warning (10268): Verilog HDL information at fen1hz.v(6): Always Construct contains both blocking and non-blocking assignments
Warning (10268): Verilog HDL information at fen1k.v(6): Always Construct contains both blocking and non-blocking assignments

💿 文件大小 307 K

👤 上传用户 sky8997991

📂 所属分类 VHDL/FPGA/Verilog

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#Verilog #9999

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