jishu0.map.summary

来自「Verilog 实现9999计数」· SUMMARY 代码 · 共 10 行

Analysis & Synthesis Status : Successful - Thu Jan 24 08:57:39 2008
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : jishu0
Top-level Entity Name : Block1
Family : MAX II
Total logic elements : 131
Total pins : 14
Total virtual pins : 0
UFM blocks : 0