jishu0.fit.rpt

Verilog 实现9999计数

+------------------------------------------------------------------------------------------------+
; Advanced Data - Placement Preparation                                                          ;
+--------------------------------------------------------------------------------+---------------+
; Name                                                                           ; Value         ;
+--------------------------------------------------------------------------------+---------------+
; Auto Fit Point 1 - Fit Attempt 1                                               ; ff            ;
; Mid Wire Use - Fit Attempt 1                                                   ; 28            ;
; Mid Slack - Fit Attempt 1                                                      ; -22311        ;
; Internal Atom Count - Fit Attempt 1                                            ; 129           ;
; LE/ALM Count - Fit Attempt 1                                                   ; 129           ;
; LAB Count - Fit Attempt 1                                                      ; 23            ;
; Outputs per Lab - Fit Attempt 1                                                ; 4.565         ;
; Inputs per LAB - Fit Attempt 1                                                 ; 4.652         ;
; Global Inputs per LAB - Fit Attempt 1                                          ; 0.609         ;
; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1       ; 0:23          ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1                                ; 0:20;1:3      ;
; LAB Constraint 'non-global controls' - Fit Attempt 1                           ; 0:12;1:11     ;
; LAB Constraint 'un-route combination' - Fit Attempt 1                          ; 0:12;1:11     ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1                    ; 0:12;1:11     ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1                     ; 0:12;1:11     ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1           ; 0:15;1:8      ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1             ; 0:23          ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1    ; 0:20;1:3      ;
; LAB Constraint 'global control signals' - Fit Attempt 1                        ; 0:10;1:12;2:1 ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1                    ; 0:10;1:10;2:3 ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1               ; 0:23          ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1                               ; 0:10;1:13     ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1                             ; 0:15;1:8      ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1                           ; 0:2;1:21      ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1                      ; 0:15;1:8      ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:23          ;
; LEs in Chains - Fit Attempt 1                                                  ; 64            ;
; LEs in Long Chains - Fit Attempt 1                                             ; 64            ;
; LABs with Chains - Fit Attempt 1                                               ; 8             ;
; LABs with Multiple Chains - Fit Attempt 1                                      ; 0             ;
; Time - Fit Attempt 1                                                           ; 0             ;
; Time in tsm_tan.dll - Fit Attempt 1                                            ; 0.016         ;
+--------------------------------------------------------------------------------+---------------+


+----------------------------------------------+
; Advanced Data - Placement                    ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Auto Fit Point 2 - Fit Attempt 1    ; ff     ;
; Early Wire Use - Fit Attempt 1      ; 6      ;
; Early Slack - Fit Attempt 1         ; -30657 ;
; Auto Fit Point 3 - Fit Attempt 1    ; ff     ;
; Auto Fit Point 4 - Fit Attempt 1    ; ff     ;
; Mid Wire Use - Fit Attempt 1        ; 14     ;
; Mid Slack - Fit Attempt 1           ; -28949 ;
; Late Wire Use - Fit Attempt 1       ; 15     ;
; Late Slack - Fit Attempt 1          ; -28949 ;
; Auto Fit Point 5 - Fit Attempt 1    ; ff     ;
; Time - Fit Attempt 1                ; 0      ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.297  ;
+-------------------------------------+--------+


+----------------------------------------------+
; Advanced Data - Routing                      ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Early Slack - Fit Attempt 1         ; -27706 ;
; Early Wire Use - Fit Attempt 1      ; 12     ;
; Peak Regional Wire - Fit Attempt 1  ; 11     ;
; Mid Slack - Fit Attempt 1           ; -28844 ;
; Late Slack - Fit Attempt 1          ; -28691 ;
; Late Slack - Fit Attempt 1          ; -28691 ;
; Late Wire Use - Fit Attempt 1       ; 16     ;
; Time - Fit Attempt 1                ; 1      ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.437  ;
+-------------------------------------+--------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Thu Jan 24 08:57:46 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off jishu0 -c jishu0
Info: Selected device EPM240T100C5 for design "jishu0"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM240T100I5 is compatible
    Info: Device EPM570T100C5 is compatible
    Info: Device EPM570T100I5 is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Assuming a global tsu requirement of 2.0 ns
    Info: Assuming a global tco requirement of 1.0 ns
    Info: Assuming a global tpd requirement of 1.0 ns
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk_in0" to use Global clock in PIN 12
Info: Automatically promoted signal "fen1k:inst|f1k" to use Global clock
Info: Automatically promoted signal "fen1hz:inst7|f1hz" to use Global clock
Info: Automatically promoted some destinations of signal "jishu1:inst2|cy1" to use Global clock
    Info: Destination "jishu1:inst2|cy1" may be non-global or may not use global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to pin delay of 9.349 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X4_Y1; Fanout = 5; REG Node = 'jishu1:inst2|qh2[2]'
    Info: 2: + IC(0.845 ns) + CELL(0.511 ns) = 1.356 ns; Loc. = LAB_X4_Y1; Fanout = 1; COMB Node = 'mux:inst5|Selector1~239'
    Info: 3: + IC(0.980 ns) + CELL(0.200 ns) = 2.536 ns; Loc. = LAB_X4_Y1; Fanout = 8; COMB Node = 'mux:inst5|Selector1~240'
    Info: 4: + IC(1.726 ns) + CELL(0.511 ns) = 4.773 ns; Loc. = LAB_X6_Y1; Fanout = 1; COMB Node = 'yima:inst4|WideOr6~23'
    Info: 5: + IC(2.254 ns) + CELL(2.322 ns) = 9.349 ns; Loc. = PIN_16; Fanout = 0; PIN Node = 'q[1]'
    Info: Total cell delay = 3.544 ns ( 37.91 % )
    Info: Total interconnect delay = 5.805 ns ( 62.09 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 10% of the available device resources. Peak interconnect usage is 10%
    Info: The peak interconnect region extends from location x0_y0 to location x8_y5
Info: Fitter routing operations ending: elapsed time is 00:00:01
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
    Info: Pin d_out[1] has VCC driving its datain port
Info: Quartus II Fitter was successful. 0 errors, 1 warning
    Info: Processing ended: Thu Jan 24 08:57:57 2008
    Info: Elapsed time: 00:00:11


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in F:/寒假/写好的EDA程序/新建文件夹/9999/jishu0.fit.smsg.