fen1hz.v

Verilog 实现9999计数

module fen1hz(clk_0,f1hz);
input clk_0;
output f1hz;
reg f1hz;
integer cn;
always@(posedge clk_0)
begin
   if(cn<999)
  begin
     cn=cn+1;
     f1hz<=1'b0;
  end
   else
     begin
       cn=0;
       f1hz<=1'b1;
     end
end
endmodule