mux.v

Verilog 实现9999计数

module mux(dis_select,low,hig,hig2,hig3,hig4,out);
input[2:0]dis_select;
input[3:0]low,hig,hig2,hig3,hig4;
output[3:0]out;
reg[3:0]out;
always
begin
    case(dis_select)
   3'b000:out<=low;
   3'b001:out<=hig;
   3'b010:out<=hig2;
   3'b011:out<=hig3;
   3'b100:out<=hig4;
  //3'b101:out<=hig5;
   default:out<=4'bzzzz;
   endcase
end
endmodule