dispselect.v

Verilog 实现9999计数

module dispselect(clk2,wei,wei_out);
input clk2;
output[2:0]wei;
output[4:0]wei_out;
reg[2:0]wei;
reg[4:0]wei_out;
always@(posedge clk2)
begin
    if(wei<3'b011)
    wei<=wei+1;
    else
    wei<=3'b000;
   case(wei)
 3'b000:wei_out<=5'b01111;//共阴极，位是低电平选通
 3'b001:wei_out<=5'b10111;
 3'b010:wei_out<=5'b11011;
 3'b011:wei_out=5'b11110;
default:wei_out=5'bzzzz;
 endcase
   end 
endmodule