jishu0.map.rpt

Verilog 实现9999计数

;     -- asynchronous clear/load mode         ; 0              ;
;                                             ;                ;
; Total registers                             ; 89             ;
; Total logic cells in carry chains           ; 64             ;
; I/O pins                                    ; 14             ;
; Maximum fan-out node                        ; fen1k:inst|f1k ;
; Maximum fan-out                             ; 39             ;
; Total fan-out                               ; 525            ;
; Average fan-out                             ; 3.62           ;
+---------------------------------------------+----------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                        ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name      ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------+
; |Block1                    ; 131 (0)     ; 89           ; 0          ; 14   ; 0            ; 42 (0)       ; 2 (0)             ; 87 (0)           ; 64 (0)          ; 0 (0)      ; |Block1                  ;
;    |dispselect:inst1|      ; 6 (6)       ; 6            ; 0          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 6 (6)            ; 0 (0)           ; 0 (0)      ; |Block1|dispselect:inst1 ;
;    |fen1hz:inst7|          ; 44 (44)     ; 33           ; 0          ; 0    ; 0            ; 11 (11)      ; 1 (1)             ; 32 (32)          ; 32 (32)         ; 0 (0)      ; |Block1|fen1hz:inst7     ;
;    |fen1k:inst|            ; 45 (45)     ; 33           ; 0          ; 0    ; 0            ; 12 (12)      ; 1 (1)             ; 32 (32)          ; 32 (32)         ; 0 (0)      ; |Block1|fen1k:inst       ;
;    |jishu1:inst2|          ; 20 (20)     ; 17           ; 0          ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 17 (17)          ; 0 (0)           ; 0 (0)      ; |Block1|jishu1:inst2     ;
;    |mux:inst5|             ; 8 (8)       ; 0            ; 0          ; 0    ; 0            ; 8 (8)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Block1|mux:inst5        ;
;    |yima:inst4|            ; 8 (8)       ; 0            ; 0          ; 0    ; 0            ; 8 (8)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |Block1|yima:inst4       ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 89    ;
; Number of registers using Synchronous Clear  ; 64    ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 6     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                            ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output  ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+
; 5:1                ; 4 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; No         ; |Block1|mux:inst5|Selector3 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+


+-------------------------------------------+
; Source assignments for dispselect:inst1   ;
+----------------+-------+------+-----------+
; Assignment     ; Value ; From ; To        ;
+----------------+-------+------+-----------+
; POWER_UP_LEVEL ; Low   ; -    ; always0~  ;
; POWER_UP_LEVEL ; Low   ; -    ; always0~  ;
; POWER_UP_LEVEL ; Low   ; -    ; always0~  ;
; POWER_UP_LEVEL ; Low   ; -    ; always0~  ;
; POWER_UP_LEVEL ; Low   ; -    ; always0~  ;
+----------------+-------+------+-----------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Thu Jan 24 08:57:32 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off jishu0 -c jishu0
Warning: Can't analyze file -- file F:/寒假/写好的EDA程序/新建文件夹/9999/jishu0.v is missing
Info: Found 1 design units, including 1 entities, in source file yima.v
    Info: Found entity 1: yima
Info: Found 1 design units, including 1 entities, in source file dis.v
    Info: Found entity 1: dis
Info: Found 1 design units, including 1 entities, in source file fegpin.v
    Info: Found entity 1: fen
Warning: Can't analyze file -- file F:/寒假/写好的EDA程序/新建文件夹/9999/fengpin1.v is missing
Info: Found 1 design units, including 1 entities, in source file Block1.bdf
    Info: Found entity 1: Block1
Warning: Entity "mux" obtained from "F:/寒假/写好的EDA程序/新建文件夹/9999/mux.v" instead of from Quartus II megafunction library
Info: Found 1 design units, including 1 entities, in source file mux.v
    Info: Found entity 1: mux
Info: Found 1 design units, including 1 entities, in source file dispselect.v
    Info: Found entity 1: dispselect
Info: Found 1 design units, including 1 entities, in source file fen1hz.v
    Info: Found entity 1: fen1hz
Info: Found 1 design units, including 1 entities, in source file fen1k.v
    Info: Found entity 1: fen1k
Warning: Can't analyze file -- file F:/寒假/写好的EDA程序/新建文件夹/9999/ji.v is missing
Info: Found 1 design units, including 1 entities, in source file jishu1.v
    Info: Found entity 1: jishu1
Info: Elaborating entity "Block1" for the top level hierarchy
Warning: Found multiple base names
Warning: Found multiple base names
Warning: Found multiple base names
Info: Elaborating entity "dispselect" for hierarchy "dispselect:inst1"
Warning (10230): Verilog HDL assignment warning at dispselect.v(10): truncated value with size 32 to match size of target (3)
Info: Elaborating entity "fen1k" for hierarchy "fen1k:inst"
Info: Elaborating entity "yima" for hierarchy "yima:inst4"
Info: Elaborating entity "mux" for hierarchy "mux:inst5"
Info: Elaborating entity "jishu1" for hierarchy "jishu1:inst2"
Warning (10036): Verilog HDL or VHDL warning at jishu1.v(5): object "cy3" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at jishu1.v(16): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at jishu1.v(20): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at jishu1.v(34): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at jishu1.v(38): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at jishu1.v(49): truncated value with size 32 to match size of target (4)
Info: Elaborating entity "fen1hz" for hierarchy "fen1hz:inst7"
Info: Power-up level of register "dispselect:inst1|wei_out[1]~reg0" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "dispselect:inst1|wei_out[1]~reg0" with stuck data_in port to stuck value VCC
Warning: Converted TRI buffer or tri-state bus to logic, or removed OPNDRN
    Warning: Converting TRI node "mux:inst5|out[3]" that feeds logic to a wire
    Warning: Converting TRI node "mux:inst5|out[2]" that feeds logic to a wire
    Warning: Converting TRI node "mux:inst5|out[1]" that feeds logic to a wire
    Warning: Converting TRI node "mux:inst5|out[0]" that feeds logic to a wire
Info: Duplicate registers merged to single register
    Info: Duplicate register "dispselect:inst1|always0~5" merged to single register "dispselect:inst1|always0~0"
    Info: Duplicate register "dispselect:inst1|always0~1" merged to single register "dispselect:inst1|always0~0"
    Info: Duplicate register "dispselect:inst1|always0~3" merged to single register "dispselect:inst1|always0~0"
    Info: Duplicate register "dispselect:inst1|always0~7" merged to single register "dispselect:inst1|always0~0"
Warning: Reduced register "dispselect:inst1|wei[2]" with stuck data_in port to stuck value GND
Info: Power-up level of register "dispselect:inst1|always0~0" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "dispselect:inst1|always0~0" with stuck data_in port to stuck value VCC
Warning: Removed always-enabled tri-state buffer dispselect:inst1|wei_out[4] feeding logic, open-drain buffer, or output pin
Warning: Removed always-enabled tri-state buffer dispselect:inst1|wei_out[3] feeding logic, open-drain buffer, or output pin
Warning: Removed always-enabled tri-state buffer dispselect:inst1|wei_out[2] feeding logic, open-drain buffer, or output pin
Warning: Removed always-enabled tri-state buffer dispselect:inst1|wei_out[1] feeding logic, open-drain buffer, or output pin
Warning: Removed always-enabled tri-state buffer dispselect:inst1|wei_out[0] feeding logic, open-drain buffer, or output pin
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "d_out[1]" stuck at VCC
Info: Implemented 145 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 13 output pins
    Info: Implemented 131 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 29 warnings
    Info: Processing ended: Thu Jan 24 08:57:39 2008
    Info: Elapsed time: 00:00:07


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in F:/寒假/写好的EDA程序/新建文件夹/9999/jishu0.map.smsg.