jishu1.v

Verilog 实现9999计数

module jishu1(clk_0,qlow,qh1,qh2,qh3,qh4);
input clk_0;
output[3:0]qlow,qh1,qh2,qh3,qh4;
reg[3:0]qlow,qh1,qh2,qh3,qh4;
reg cy1,cy2,cy3;
always@(posedge clk_0)
     if(qlow==9)
   begin
      qlow<=0;
     if(qh1==9)
    begin
     qh1<=0;
     cy1<=1;
     end
   else
     qh1<=qh1+1; 
end
else
  begin
    qlow<=qlow+1;
     cy1<=0;
  end
always@(posedge cy1)
//begin
  if(qh2==9)
 begin
    qh2<=0;
      if(qh3==9)
       begin
        qh3<=0;
        cy2<=1;
        end
  else
    qh3<=qh3+1;
end
else
    begin
     qh2<=qh2+1;
     cy2<=0;
     end
always@(posedge cy2)
    if(qh4==9)
     begin
      qh4<=0;
      cy3<=1;
     end
  else
     begin
      qh4<=qh4+1;
      cy3<=0;
     end
endmodule