io_lvpecl_synopsys.vhd

基于VHDL语言的低压差分接口规范的实现

    O, OB : out std_logic
  );
end entity OBUFTDS_FDSE_LVPECL;

architecture lvpecl_buff0 of OBUFTDS_FDSE_lvpecl is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute off_p IOB "true" -type string
-- set_attribute off_n IOB "true" -type string
-- set_attribute tri_p IOB "true" -type string
-- set_attribute tri_n IOB "true" -type string
-- synopsys dc_script_end
  signal D_n, q_n, q_p, t_p, t_n : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDSE port map (D => D, CE => CE, C => C, S => S, Q => q_p);
  off_n : FDRE port map (D => D_n, CE => CE, C => C, R => S, Q => q_n);
  tri_p : FDSE port map (D => T, CE => CE, C => C, S => S, Q => t_p);
  tri_n : FDSE port map (D => T, CE => CE, C => C, S => S, Q => t_n);
  pad_p : OBUFT_LVPECL port map (I => q_p, T => t_p, O => O);
  pad_n : OBUFT_LVPECL port map (I => q_n, T => t_n, O => OB);
end lvpecl_buff0; -- OBUFTDS_FDSE_lvpecl

-- ************************
-- Tri-state output latches
-- ************************

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFTDS_LD_LVPECL is
  port (
    D, T, G : in std_logic;
    O, OB : out std_logic
  );
end entity OBUFTDS_LD_LVPECL;

architecture lvpecl_buff0 of OBUFTDS_LD_lvpecl is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute olatch_p IOB "true" -type string
-- set_attribute olatch_n IOB "true" -type string
-- set_attribute tri_p IOB "true" -type string
-- set_attribute tri_n IOB "true" -type string
-- synopsys dc_script_end
  signal D_n, q_n, q_p, t_p, t_n, CLR : std_logic;
begin
  CLR <= '0';
  inv_n : INV port map (I => D, O => D_n);
  olatch_p : LDC port map (D => D, G => G, CLR => CLR, Q => q_p);
  olatch_n : LDP port map (D => D_n, G => G, PRE => CLR, Q => q_n);
  tri_p : LDP port map (D => T, G => G, PRE => CLR, Q => t_p);
  tri_n : LDP port map (D => T, G => G, PRE => CLR, Q => t_n);
  pad_p : OBUFT_LVPECL port map (I => q_p, T => t_p, O => O);
  pad_n : OBUFT_LVPECL port map (I => q_n, T => t_n, O => OB);
end lvpecl_buff0; -- OBUFTDS_LD_lvpecl

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFTDS_LDE_LVPECL is
  port (
    D, T, GE, G : in std_logic;
    O, OB : out std_logic
  );
end entity OBUFTDS_LDE_LVPECL;

architecture lvpecl_buff0 of OBUFTDS_LDE_lvpecl is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute olatch_p IOB "true" -type string
-- set_attribute olatch_n IOB "true" -type string
-- set_attribute tri_p IOB "true" -type string
-- set_attribute tri_n IOB "true" -type string
-- synopsys dc_script_end
  signal D_n, q_n, q_p, t_p, t_n, CLR : std_logic;
begin
  CLR <= '0';
  inv_n : INV port map (I => D, O => D_n);
  olatch_p : LDCE port map (D => D, GE => GE, G => G, CLR => CLR, Q => q_p);
  olatch_n : LDPE port map (D => D_n, GE => GE, G => G, PRE => CLR, Q => q_n);
  tri_p : LDPE port map (D => T, GE => GE, G => G, PRE => CLR, Q => t_p);
  tri_n : LDPE port map (D => T, GE => GE, G => G, PRE => CLR, Q => t_n);
  pad_p : OBUFT_LVPECL port map (I => q_p, T => t_p, O => O);
  pad_n : OBUFT_LVPECL port map (I => q_n, T => t_n, O => OB);
end lvpecl_buff0; -- OBUFTDS_LDE_lvpecl

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFTDS_LDC_LVPECL is
  port (
    D, T, G, CLR : in std_logic;
    O, OB : out std_logic
  );
end entity OBUFTDS_LDC_LVPECL;

architecture lvpecl_buff0 of OBUFTDS_LDC_lvpecl is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute olatch_p IOB "true" -type string
-- set_attribute olatch_n IOB "true" -type string
-- set_attribute tri_p IOB "true" -type string
-- set_attribute tri_n IOB "true" -type string
-- synopsys dc_script_end
  signal D_n, q_n, q_p, t_p, t_n : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  olatch_p : LDC port map (D => D, G => G, CLR => CLR, Q => q_p);
  olatch_n : LDP port map (D => D_n, G => G, PRE => CLR, Q => q_n);
  tri_p : LDP port map (D => T, G => G, PRE => CLR, Q => t_p);
  tri_n : LDP port map (D => T, G => G, PRE => CLR, Q => t_n);
  pad_p : OBUFT_LVPECL port map (I => q_p, T => t_p, O => O);
  pad_n : OBUFT_LVPECL port map (I => q_n, T => t_n, O => OB);
end lvpecl_buff0; -- OBUFTDS_LDC_lvpecl

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFTDS_LDCE_LVPECL is
  port (
    D, T, GE, G, CLR : in std_logic;
    O, OB : out std_logic
  );
end entity OBUFTDS_LDCE_LVPECL;

architecture lvpecl_buff0 of OBUFTDS_LDCE_lvpecl is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute olatch_p IOB "true" -type string
-- set_attribute olatch_n IOB "true" -type string
-- set_attribute tri_p IOB "true" -type string
-- set_attribute tri_n IOB "true" -type string
-- synopsys dc_script_end
  signal D_n, q_n, q_p, t_p, t_n : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  olatch_p : LDCE port map (D => D, GE => GE, G => G, CLR => CLR, Q => q_p);
  olatch_n : LDPE port map (D => D_n, GE => GE, G => G, PRE => CLR, Q => q_n);
  tri_p : LDPE port map (D => T, GE => GE, G => G, PRE => CLR, Q => t_p);
  tri_n : LDPE port map (D => T, GE => GE, G => G, PRE => CLR, Q => t_n);
  pad_p : OBUFT_LVPECL port map (I => q_p, T => t_p, O => O);
  pad_n : OBUFT_LVPECL port map (I => q_n, T => t_n, O => OB);
end lvpecl_buff0; -- OBUFTDS_LDCE_lvpecl

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFTDS_LDP_LVPECL is
  port (
    D, T, G, PRE : in std_logic;
    O, OB : out std_logic
  );
end entity OBUFTDS_LDP_LVPECL;

architecture lvpecl_buff0 of OBUFTDS_LDP_lvpecl is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute olatch_p IOB "true" -type string
-- set_attribute olatch_n IOB "true" -type string
-- set_attribute tri_p IOB "true" -type string
-- set_attribute tri_n IOB "true" -type string
-- synopsys dc_script_end
  signal D_n, q_n, q_p, t_p, t_n : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  olatch_p : LDP port map (D => D, G => G, PRE => PRE, Q => q_p);
  olatch_n : LDC port map (D => D_n, G => G, CLR => PRE, Q => q_n);
  tri_p : LDP port map (D => T, G => G, PRE => PRE, Q => t_p);
  tri_n : LDP port map (D => T, G => G, PRE => PRE, Q => t_n);
  pad_p : OBUFT_LVPECL port map (I => q_p, T => t_p, O => O);
  pad_n : OBUFT_LVPECL port map (I => q_n, T => t_n, O => OB);
end lvpecl_buff0; -- OBUFTDS_LDP_lvpecl

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFTDS_LDPE_LVPECL is
  port (
    D, T, GE, G, PRE : in std_logic;
    O, OB : out std_logic
  );
end entity OBUFTDS_LDPE_LVPECL;

architecture lvpecl_buff0 of OBUFTDS_LDPE_lvpecl is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute olatch_p IOB "true" -type string
-- set_attribute olatch_n IOB "true" -type string
-- set_attribute tri_p IOB "true" -type string
-- set_attribute tri_n IOB "true" -type string
-- synopsys dc_script_end
  signal D_n, q_n, q_p, t_p, t_n : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  olatch_p : LDPE port map (D => D, GE => GE, G => G, PRE => PRE, Q => q_p);
  olatch_n : LDCE port map (D => D_n, GE => GE, G => G, CLR => PRE, Q => q_n);
  tri_p : LDPE port map (D => T, GE => GE, G => G, PRE => PRE, Q => t_p);
  tri_n : LDPE port map (D => T, GE => GE, G => G, PRE => PRE, Q => t_n);
  pad_p : OBUFT_LVPECL port map (I => q_p, T => t_p, O => O);
  pad_n : OBUFT_LVPECL port map (I => q_n, T => t_n, O => OB);
end lvpecl_buff0; -- OBUFTDS_LDPE_lvpecl

-- *********************************
-- Start of the Input/Output Buffers
-- IO Buffer Flipflops
-- *********************************

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity IOBUFDS_FD_LVPECL is
  port (
    D, T, C : in std_logic;
    Q : out std_logic;
    IO, IOB : inout std_logic
  );
end entity IOBUFDS_FD_LVPECL;

architecture lvpecl_buff0 of IOBUFDS_FD_lvpecl is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute off_p IOB "true" -type string
-- set_attribute off_n IOB "true" -type string
-- set_attribute tri_p IOB "true" -type string
-- set_attribute tri_n IOB "true" -type string
-- set_attribute iff_p IOB "true" -type string
-- synopsys dc_script_end
  signal dummy_o, D_n, q_n, q_p, t_p, t_n, i_p, CLR : std_logic;
begin
  CLR <= '0';
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDC port map (D => D, C => C, CLR => CLR, Q => q_p);
  off_n : FDP port map (D => D_n, C => C, PRE => CLR, Q => q_n);
  tri_p : FDP port map (D => T, C => C, PRE => CLR, Q => t_p);
  tri_n : FDP port map (D => T, C => C, PRE => CLR, Q => t_n);
  iff_p : FD port map (D => i_p, C => C, Q => Q);
  pad_p : IOBUF_LVPECL port map (I => q_p, T => t_p, O => i_p, IO => IO);
  pad_n : IOBUF_LVPECL port map (I => q_n, T => t_n, O => dummy_o, IO => IOB);
end lvpecl_buff0; -- IOBUFDS_FD_lvpecl

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity IOBUFDS_FDE_LVPECL is
  port (
    D, T, CE, C : in std_logic;
    Q : out std_logic;
    IO, IOB : inout std_logic
  );
end entity IOBUFDS_FDE_LVPECL;

architecture lvpecl_buff0 of IOBUFDS_FDE_lvpecl is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute off_p IOB "true" -type string
-- set_attribute off_n IOB "true" -type string
-- set_attribute tri_p IOB "true" -type string
-- set_attribute tri_n IOB "true" -type string
-- set_attribute iff_p IOB "true" -type string
-- synopsys dc_script_end
  signal dummy_o, D_n, q_n, q_p, t_p, t_n, i_p, CLR : std_logic;
begin
  CLR <= '0';
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDCE port map (D => D, CE => CE, C => C, CLR => CLR, Q => q_p);
  off_n : FDPE port map (D => D_n, CE => CE, C => C, PRE => CLR, Q => q_n);
  tri_p : FDPE port map (D => T, CE => CE, C => C, PRE => CLR, Q => t_p);
  tri_n : FDPE port map (D => T, CE => CE, C => C, PRE => CLR, Q => t_n);
  iff_p : FDE port map (D => i_p, CE => CE, C => C, Q => Q);
  pad_p : IOBUF_LVPECL port map (I => q_p, T => t_p, O => i_p, IO => IO);
  pad_n : IOBUF_LVPECL port map (I => q_n, T => t_n, O => dummy_o, IO => IOB);
end lvpecl_buff0; -- IOBUFDS_FDE_lvpecl

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity IOBUFDS_FDC_LVPECL is
  port (
    D, T, C, CLR : in std_logic;
    Q : out std_logic;
    IO, IOB : inout std_logic
  );
end entity IOBUFDS_FDC_LVPECL;

architecture lvpecl_buff0 of IOBUFDS_FDC_lvpecl is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute off_p IOB "true" -type string
-- set_attribute off_n IOB "true" -type string
-- set_attribute tri_p IOB "true" -type string
-- set_attribute tri_n IOB "true" -type string
-- set_attribute iff_p IOB "true" -type string
-- synopsys dc_script_end
  signal dummy_o, D_n, q_n, q_p, t_p, t_n, i_p : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDC port map (D => D, C => C, CLR => CLR, Q => q_p);
  off_n : FDP port map (D => D_n, C => C, PRE => CLR, Q => q_n);
  tri_p : FDP port map (D => T, C => C, PRE => CLR, Q => t_p);
  tri_n : FDP port map (D => T, C => C, PRE => CLR, Q => t_n);
  iff_p : FDC port map (D => i_p, C => C, CLR => CLR, Q => Q);
  pad_p : IOBUF_LVPECL port map (I => q_p, T => t_p, O => i_p, IO => IO);
  pad_n : IOBUF_LVPECL port map (I => q_n, T => t_n, O => dummy_o, IO => IOB);
end lvpecl_buff0; -- IOBUFDS_FDC_lvpecl

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity IOBUFDS_FDCE_LVPECL is
  port (
    D, T, CE, C, CLR : in std_logic;
    Q : out std_logic;
    IO, IOB : inout std_logic
  );
end entity IOBUFDS_FDCE_LVPECL;

architecture lvpecl_buff0 of IOBUFDS_FDCE_lvpecl is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute off_p IOB "true" -type string
-- set_attribute off_n IOB "true" -type string
-- set_attribute tri_p IOB "true" -type string
-- set_attribute tri_n IOB "true" -type string
-- set_attribute iff_p IOB "true" -type string
-- synopsys dc_script_end
  signal dummy_o, D_n, q_n, q_p, t_p, t_n, i_p : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDCE port map (D => D, CE => CE, C => C, CLR => CLR, Q => q_p);
  off_n : FDPE port map (D => D_n, CE => CE, C => C, PRE => CLR, Q => q_n);
  tri_p : FDPE port map (D => T, CE => CE, C => C, PRE => CLR, Q => t_p);
  tri_n : FDPE port map (D => T, CE => CE, C => C, PRE => CLR, Q => t_n);
  iff_p : FDCE port map (D => i_p, CE => CE, C => C, CLR => CLR, Q => Q);
  pad_p : IOBUF_LVPECL port map (I => q_p, T => t_p, O => i_p, IO => IO);
  pad_n : IOBUF_LVPECL port map (I => q_n, T => t_n, O => dummy_o, IO => IOB);
end lvpecl_buff0; -- IOBUFDS_FDCE_lvpecl

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity IOBUFDS_FDP_LVPECL is
  port (
    D, T, C, PRE : in std_logic;
    Q : out std_logic;
    IO, IOB : inout std_logic
  );
end entity IOBUFDS_FDP_LVPECL;

architecture lvpecl_buff0 of IOBUFDS_FDP_lvpecl is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute off_p IOB "true" -type string
-- set_attribute off_n IOB "true" -type string
-- set_attribute tri_p IOB "true" -type string
-- set_attribute tri_n IOB "true" -type string
-- set_attribute iff_p IOB "true" -type string