io_lvpecl_synopsys.vhd

基于VHDL语言的低压差分接口规范的实现

  pad_n : OBUF_LVPECL port map (I => q_n, O => OB);
end lvpecl_buff0; -- OBUFDS_LDC_lvpecl

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFDS_LDCE_LVPECL is
  port (
    D, GE, G, CLR : in std_logic;
    O, OB : out std_logic
  );
end entity OBUFDS_LDCE_LVPECL;

architecture lvpecl_buff0 of OBUFDS_LDCE_lvpecl is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute olatch_p IOB "true" -type string
-- set_attribute olatch_n IOB "true" -type string
-- synopsys dc_script_end
  signal D_n, q_n, q_p : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  olatch_p : LDCE port map (D => D, GE => GE, G => G, CLR => CLR, Q => q_p);
  olatch_n : LDPE port map (D => D_n, GE => GE, G => G, PRE => CLR, Q => q_n);
  pad_p : OBUF_LVPECL port map (I => q_p , O => O);
  pad_n : OBUF_LVPECL port map (I => q_n, O => OB);
end lvpecl_buff0; -- OBUFDS_LDCE_lvpecl

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFDS_LDP_LVPECL is
  port (
    D, G, PRE : in std_logic;
    O, OB : out std_logic
  );
end entity OBUFDS_LDP_LVPECL;

architecture lvpecl_buff0 of OBUFDS_LDP_lvpecl is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute olatch_p IOB "true" -type string
-- set_attribute olatch_n IOB "true" -type string
-- synopsys dc_script_end
  signal D_n, q_n, q_p : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  olatch_p : LDP port map (D => D, G => G, PRE => PRE, Q => q_p);
  olatch_n : LDC port map (D => D_n, G => G, CLR => PRE, Q => q_n);
  pad_p : OBUF_LVPECL port map (I => q_p , O => O);
  pad_n : OBUF_LVPECL port map (I => q_n, O => OB);
end lvpecl_buff0; -- OBUFDS_LDP_lvpecl

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFDS_LDPE_LVPECL is
  port (
    D, GE, G, PRE : in std_logic;
    O, OB : out std_logic
  );
end entity OBUFDS_LDPE_LVPECL;

architecture lvpecl_buff0 of OBUFDS_LDPE_lvpecl is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute olatch_p IOB "true" -type string
-- set_attribute olatch_n IOB "true" -type string
-- synopsys dc_script_end
  signal D_n, q_n, q_p : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  olatch_p : LDPE port map (D => D, GE => GE, G => G, PRE => PRE, Q => q_p);
  olatch_n : LDCE port map (D => D_n, GE => GE, G => G, CLR => PRE, Q => q_n);
  pad_p : OBUF_LVPECL port map (I => q_p , O => O);
  pad_n : OBUF_LVPECL port map (I => q_n, O => OB);
end lvpecl_buff0; -- OBUFDS_LDPE_lvpecl


-- *************************************
-- Start of the Tri-State Output Buffers
-- Tri-state output flipflops
-- *************************************

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFTDS_FD_LVPECL is
  port (
    D, T, C : in std_logic;
    O, OB : out std_logic
  );
end entity OBUFTDS_FD_LVPECL;

architecture lvpecl_buff0 of OBUFTDS_FD_lvpecl is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute off_p IOB "true" -type string
-- set_attribute off_n IOB "true" -type string
-- set_attribute tri_p IOB "true" -type string
-- set_attribute tri_n IOB "true" -type string
-- synopsys dc_script_end
  signal D_n, q_n, q_p, t_p, t_n, CLR : std_logic;
begin
  CLR <= '0';
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDC port map (D => D, C => C, CLR => CLR, Q => q_p);
  off_n : FDP port map (D => D_n, C => C, PRE => CLR, Q => q_n);
  tri_p : FDP port map (D => T, C => C, PRE => CLR, Q => t_p);
  tri_n : FDP port map (D => T, C => C, PRE => CLR, Q => t_n);
  pad_p : OBUFT_LVPECL port map (I => q_p, T => t_p, O => O);
  pad_n : OBUFT_LVPECL port map (I => q_n, T => t_n, O => OB);
end lvpecl_buff0; -- OBUFTDS_FD_lvpecl

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFTDS_FDE_LVPECL is
  port (
    D, T, CE, C : in std_logic;
    O, OB : out std_logic
  );
end entity OBUFTDS_FDE_LVPECL;

architecture lvpecl_buff0 of OBUFTDS_FDE_lvpecl is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute off_p IOB "true" -type string
-- set_attribute off_n IOB "true" -type string
-- set_attribute tri_p IOB "true" -type string
-- set_attribute tri_n IOB "true" -type string
-- synopsys dc_script_end
  signal D_n, q_n, q_p, t_p, t_n, CLR : std_logic;
begin
  CLR <= '0';
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDCE port map (D => D, CE => CE, C => C, CLR => CLR, Q => q_p);
  off_n : FDPE port map (D => D_n, CE => CE, C => C, PRE => CLR, Q => q_n);
  tri_p : FDPE port map (D => T, CE => CE, C => C, PRE => CLR, Q => t_p);
  tri_n : FDPE port map (D => T, CE => CE, C => C, PRE => CLR, Q => t_n);
  pad_p : OBUFT_LVPECL port map (I => q_p, T => t_p, O => O);
  pad_n : OBUFT_LVPECL port map (I => q_n, T => t_n, O => OB);
end lvpecl_buff0; -- OBUFTDS_FDE_lvpecl

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFTDS_FDC_LVPECL is
  port (
    D, T, C, CLR : in std_logic;
    O, OB : out std_logic
  );
end entity OBUFTDS_FDC_LVPECL;

architecture lvpecl_buff0 of OBUFTDS_FDC_lvpecl is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute off_p IOB "true" -type string
-- set_attribute off_n IOB "true" -type string
-- set_attribute tri_p IOB "true" -type string
-- set_attribute tri_n IOB "true" -type string
-- synopsys dc_script_end
  signal D_n, q_n, q_p, t_p, t_n : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDC port map (D => D, C => C, CLR => CLR, Q => q_p);
  off_n : FDP port map (D => D_n, C => C, PRE => CLR, Q => q_n);
  tri_p : FDP port map (D => T, C => C, PRE => CLR, Q => t_p);
  tri_n : FDP port map (D => T, C => C, PRE => CLR, Q => t_n);
  pad_p : OBUFT_LVPECL port map (I => q_p, T => t_p, O => O);
  pad_n : OBUFT_LVPECL port map (I => q_n, T => t_n, O => OB);
end lvpecl_buff0; -- OBUFTDS_FDC_lvpecl

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFTDS_FDCE_LVPECL is
  port (
    D, T, CE, C, CLR : in std_logic;
    O, OB : out std_logic
  );
end entity OBUFTDS_FDCE_LVPECL;

architecture lvpecl_buff0 of OBUFTDS_FDCE_lvpecl is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute off_p IOB "true" -type string
-- set_attribute off_n IOB "true" -type string
-- set_attribute tri_p IOB "true" -type string
-- set_attribute tri_n IOB "true" -type string
-- synopsys dc_script_end
  signal D_n, q_n, q_p, t_p, t_n : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDCE port map (D => D, CE => CE, C => C, CLR => CLR, Q => q_p);
  off_n : FDPE port map (D => D_n, CE => CE, C => C, PRE => CLR, Q => q_n);
  tri_p : FDPE port map (D => T, CE => CE, C => C, PRE => CLR, Q => t_p);
  tri_n : FDPE port map (D => T, CE => CE, C => C, PRE => CLR, Q => t_n);
  pad_p : OBUFT_LVPECL port map (I => q_p, T => t_p, O => O);
  pad_n : OBUFT_LVPECL port map (I => q_n, T => t_n, O => OB);
end lvpecl_buff0; -- OBUFTDS_FDCE_lvpecl

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFTDS_FDP_LVPECL is
  port (
    D, T, C, PRE : in std_logic;
    O, OB : out std_logic
  );
end entity OBUFTDS_FDP_LVPECL;

architecture lvpecl_buff0 of OBUFTDS_FDP_lvpecl is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute off_p IOB "true" -type string
-- set_attribute off_n IOB "true" -type string
-- set_attribute tri_p IOB "true" -type string
-- set_attribute tri_n IOB "true" -type string
-- synopsys dc_script_end
  signal D_n, q_n, q_p, t_p, t_n : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDP port map (D => D, C => C, PRE => PRE, Q => q_p);
  off_n : FDC port map (D => D_n, C => C, CLR => PRE, Q => q_n);
  tri_p : FDP port map (D => T, C => C, PRE => PRE, Q => t_p);
  tri_n : FDP port map (D => T, C => C, PRE => PRE, Q => t_n);
  pad_p : OBUFT_LVPECL port map (I => q_p, T => t_p, O => O);
  pad_n : OBUFT_LVPECL port map (I => q_n, T => t_n, O => OB);
end lvpecl_buff0; -- OBUFTDS_FDP_lvpecl

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFTDS_FDPE_LVPECL is
  port (
    D, T, CE, C, PRE : in std_logic;
    O, OB : out std_logic
  );
end entity OBUFTDS_FDPE_LVPECL;

architecture lvpecl_buff0 of OBUFTDS_FDPE_lvpecl is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute off_p IOB "true" -type string
-- set_attribute off_n IOB "true" -type string
-- set_attribute tri_p IOB "true" -type string
-- set_attribute tri_n IOB "true" -type string
-- synopsys dc_script_end
  signal D_n, q_n, q_p, t_p, t_n : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDPE port map (D => D, CE => CE, C => C, PRE => PRE, Q => q_p);
  off_n : FDCE port map (D => D_n, CE => CE, C => C, CLR => PRE, Q => q_n);
  tri_p : FDPE port map (D => T, CE => CE, C => C, PRE => PRE, Q => t_p);
  tri_n : FDPE port map (D => T, CE => CE, C => C, PRE => PRE, Q => t_n);
  pad_p : OBUFT_LVPECL port map (I => q_p, T => t_p, O => O);
  pad_n : OBUFT_LVPECL port map (I => q_n, T => t_n, O => OB);
end lvpecl_buff0; -- OBUFTDS_FDPE_lvpecl

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFTDS_FDR_LVPECL is
  port (
    D, T, C, R : in std_logic;
    O, OB : out std_logic
  );
end entity OBUFTDS_FDR_LVPECL;

architecture lvpecl_buff0 of OBUFTDS_FDR_lvpecl is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute off_p IOB "true" -type string
-- set_attribute off_n IOB "true" -type string
-- set_attribute tri_p IOB "true" -type string
-- set_attribute tri_n IOB "true" -type string
-- synopsys dc_script_end
  signal D_n, q_n, q_p, t_p, t_n : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDR port map (D => D, C => C, R => R, Q => q_p);
  off_n : FDS port map (D => D_n, C => C, S => R, Q => q_n);
  tri_p : FDS port map (D => T, C => C, S => R, Q => t_p);
  tri_n : FDS port map (D => T, C => C, S => R, Q => t_n);
  pad_p : OBUFT_LVPECL port map (I => q_p, T => t_p, O => O);
  pad_n : OBUFT_LVPECL port map (I => q_n, T => t_n, O => OB);
end lvpecl_buff0; -- OBUFTDS_FDR_lvpecl

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFTDS_FDRE_LVPECL is
  port (
    D, T, CE, C, R : in std_logic;
    O, OB : out std_logic
  );
end entity OBUFTDS_FDRE_LVPECL;

architecture lvpecl_buff0 of OBUFTDS_FDRE_lvpecl is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute off_p IOB "true" -type string
-- set_attribute off_n IOB "true" -type string
-- set_attribute tri_p IOB "true" -type string
-- set_attribute tri_n IOB "true" -type string
-- synopsys dc_script_end
  signal D_n, q_n, q_p, t_p, t_n : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDRE port map (D => D, CE => CE, C => C, R => R, Q => q_p);
  off_n : FDSE port map (D => D_n, CE => CE, C => C, S => R, Q => q_n);
  tri_p : FDSE port map (D => T, CE => CE, C => C, S => R, Q => t_p);
  tri_n : FDSE port map (D => T, CE => CE, C => C, S => R, Q => t_n);
  pad_p : OBUFT_LVPECL port map (I => q_p, T => t_p, O => O);
  pad_n : OBUFT_LVPECL port map (I => q_n, T => t_n, O => OB);
end lvpecl_buff0; -- OBUFTDS_FDRE_lvpecl

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFTDS_FDS_LVPECL is
  port (
    D, T, C, S : in std_logic;
    O, OB : out std_logic
  );
end entity OBUFTDS_FDS_LVPECL;

architecture lvpecl_buff0 of OBUFTDS_FDS_lvpecl is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute off_p IOB "true" -type string
-- set_attribute off_n IOB "true" -type string
-- set_attribute tri_p IOB "true" -type string
-- set_attribute tri_n IOB "true" -type string
-- synopsys dc_script_end
  signal D_n, q_n, q_p, t_p, t_n : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDS port map (D => D, C => C, S => S, Q => q_p);
  off_n : FDR port map (D => D_n, C => C, R => S, Q => q_n);
  tri_p : FDS port map (D => T, C => C, S => S, Q => t_p);
  tri_n : FDS port map (D => T, C => C, S => S, Q => t_n);
  pad_p : OBUFT_LVPECL port map (I => q_p, T => t_p, O => O);
  pad_n : OBUFT_LVPECL port map (I => q_n, T => t_n, O => OB);
end lvpecl_buff0; -- OBUFTDS_FDS_lvpecl

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFTDS_FDSE_LVPECL is
  port (
    D, T, CE, C, S : in std_logic;