io_lvpecl_synopsys.vhd

基于VHDL语言的低压差分接口规范的实现

    Q : out std_logic
  );
end entity IBUFDS_LDPE_LVPECL;

architecture lvpecl_buff0 of IBUFDS_LDPE_lvpecl is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute ilatch_p IOB "true" -type string
-- synopsys dc_script_end
  signal I_w, IB_w : std_logic;
begin
  ilatch_p : LDPE port map (D => I_w, GE => GE, G => G, PRE => PRE, Q => Q);
  pad_p : IBUF_LVPECL port map (I => I, O => I_w);
  pad_n : IBUF_LVPECL port map (I => IB, O => IB_w);
end lvpecl_buff0; -- IBUFDS_LDPE_lvpecl

-- ***************************
-- Start of the Output Buffers
-- Output Flipflops
-- ***************************

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFDS_FD_LVPECL is
  port (
    D, C : in std_logic;
    O, OB : out std_logic
  );
end entity OBUFDS_FD_LVPECL;

architecture lvpecl_buff0 of OBUFDS_FD_lvpecl is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute off_p IOB "true" -type string
-- set_attribute off_n IOB "true" -type string
-- synopsys dc_script_end
  signal D_n, q_n, q_p, CLR : std_logic;
begin
  CLR <= '0';
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDC port map (D => D, C => C, CLR => CLR, Q => q_p);
  off_n : FDP port map (D => D_n, C => C, PRE => CLR, Q => q_n);
  pad_p : OBUF_LVPECL port map (I => q_p , O => O);
  pad_n : OBUF_LVPECL port map (I => q_n, O => OB);
end lvpecl_buff0; -- OBUFDS_FD_lvpecl

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFDS_FDE_LVPECL is
  port (
    D, CE, C : in std_logic;
    O, OB : out std_logic
  );
end entity OBUFDS_FDE_LVPECL;

architecture lvpecl_buff0 of OBUFDS_FDE_lvpecl is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute off_p IOB "true" -type string
-- set_attribute off_n IOB "true" -type string
-- synopsys dc_script_end
  signal D_n, q_n, q_p, CLR : std_logic;
begin
  CLR <= '0';
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDCE port map (D => D, CE => CE, C => C, CLR => CLR, Q => q_p);
  off_n : FDPE port map (D => D_n, CE => CE, C => C, PRE => CLR, Q => q_n);
  pad_p : OBUF_LVPECL port map (I => q_p , O => O);
  pad_n : OBUF_LVPECL port map (I => q_n, O => OB);
end lvpecl_buff0; -- OBUFDS_FDE_lvpecl

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFDS_FDC_LVPECL is
  port (
    D, C, CLR : in std_logic;
    O, OB : out std_logic
  );
end entity OBUFDS_FDC_LVPECL;

architecture lvpecl_buff0 of OBUFDS_FDC_lvpecl is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute off_p IOB "true" -type string
-- set_attribute off_n IOB "true" -type string
-- synopsys dc_script_end
  signal D_n, q_n, q_p : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDC port map (D => D, C => C, CLR => CLR, Q => q_p);
  off_n : FDP port map (D => D_n, C => C, PRE => CLR, Q => q_n);
  pad_p : OBUF_LVPECL port map (I => q_p , O => O);
  pad_n : OBUF_LVPECL port map (I => q_n, O => OB);
end lvpecl_buff0; -- OBUFDS_FDC_lvpecl

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFDS_FDCE_LVPECL is
  port (
    D, CE, C, CLR : in std_logic;
    O, OB : out std_logic
  );
end entity OBUFDS_FDCE_LVPECL;

architecture lvpecl_buff0 of OBUFDS_FDCE_lvpecl is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute off_p IOB "true" -type string
-- set_attribute off_n IOB "true" -type string
-- synopsys dc_script_end
  signal D_n, q_n, q_p : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDCE port map (D => D, CE => CE, C => C, CLR => CLR, Q => q_p);
  off_n : FDPE port map (D => D_n, CE => CE, C => C, PRE => CLR, Q => q_n);
  pad_p : OBUF_LVPECL port map (I => q_p , O => O);
  pad_n : OBUF_LVPECL port map (I => q_n, O => OB);
end lvpecl_buff0; -- OBUFDS_FDCE_lvpecl

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFDS_FDP_LVPECL is
  port (
    D, C, PRE : in std_logic;
    O, OB : out std_logic
  );
end entity OBUFDS_FDP_LVPECL;

architecture lvpecl_buff0 of OBUFDS_FDP_lvpecl is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute off_p IOB "true" -type string
-- set_attribute off_n IOB "true" -type string
-- synopsys dc_script_end
  signal D_n, q_n, q_p : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDP port map (D => D, C => C, PRE => PRE, Q => q_p);
  off_n : FDC port map (D => D_n, C => C, CLR => PRE, Q => q_n);
  pad_p : OBUF_LVPECL port map (I => q_p , O => O);
  pad_n : OBUF_LVPECL port map (I => q_n, O => OB);
end lvpecl_buff0; -- OBUFDS_FDP_lvpecl

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFDS_FDPE_LVPECL is
  port (
    D, CE, C, PRE : in std_logic;
    O, OB : out std_logic
  );
end entity OBUFDS_FDPE_LVPECL;

architecture lvpecl_buff0 of OBUFDS_FDPE_lvpecl is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute off_p IOB "true" -type string
-- set_attribute off_n IOB "true" -type string
-- synopsys dc_script_end
  signal D_n, q_n, q_p : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDPE port map (D => D, CE => CE, C => C, PRE => PRE, Q => q_p);
  off_n : FDCE port map (D => D_n, CE => CE, C => C, CLR => PRE, Q => q_n);
  pad_p : OBUF_LVPECL port map (I => q_p , O => O);
  pad_n : OBUF_LVPECL port map (I => q_n, O => OB);
end lvpecl_buff0; -- OBUFDS_FDPE_lvpecl

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFDS_FDR_LVPECL is
  port (
    D, C, R : in std_logic;
    O, OB : out std_logic
  );
end entity OBUFDS_FDR_LVPECL;

architecture lvpecl_buff0 of OBUFDS_FDR_lvpecl is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute off_p IOB "true" -type string
-- set_attribute off_n IOB "true" -type string
-- synopsys dc_script_end
  signal D_n, q_n, q_p : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDR port map (D => D, C => C, R => R, Q => q_p);
  off_n : FDS port map (D => D_n, C => C, S => R, Q => q_n);
  pad_p : OBUF_LVPECL port map (I => q_p , O => O);
  pad_n : OBUF_LVPECL port map (I => q_n, O => OB);
end lvpecl_buff0; -- OBUFDS_FDR_lvpecl

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFDS_FDRE_LVPECL is
  port (
    D, CE, C, R : in std_logic;
    O, OB : out std_logic
  );
end entity OBUFDS_FDRE_LVPECL;

architecture lvpecl_buff0 of OBUFDS_FDRE_lvpecl is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute off_p IOB "true" -type string
-- set_attribute off_n IOB "true" -type string
-- synopsys dc_script_end
  signal D_n, q_n, q_p : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDRE port map (D => D, CE => CE, C => C, R => R, Q => q_p);
  off_n : FDSE port map (D => D_n, CE => CE, C => C, S => R, Q => q_n);
  pad_p : OBUF_LVPECL port map (I => q_p , O => O);
  pad_n : OBUF_LVPECL port map (I => q_n, O => OB);
end lvpecl_buff0; -- OBUFDS_FDRE_lvpecl

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFDS_FDS_LVPECL is
  port (
    D, C, S : in std_logic;
    O, OB : out std_logic
  );
end entity OBUFDS_FDS_LVPECL;

architecture lvpecl_buff0 of OBUFDS_FDS_lvpecl is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute off_p IOB "true" -type string
-- set_attribute off_n IOB "true" -type string
-- synopsys dc_script_end
  signal D_n, q_n, q_p : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDS port map (D => D, C => C, S => S, Q => q_p);
  off_n : FDR port map (D => D_n, C => C, R => S, Q => q_n);
  pad_p : OBUF_LVPECL port map (I => q_p , O => O);
  pad_n : OBUF_LVPECL port map (I => q_n, O => OB);
end lvpecl_buff0; -- OBUFDS_FDS_lvpecl

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFDS_FDSE_LVPECL is
  port (
    D, CE, C, S : in std_logic;
    O, OB : out std_logic
  );
end entity OBUFDS_FDSE_LVPECL;

architecture lvpecl_buff0 of OBUFDS_FDSE_lvpecl is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute off_p IOB "true" -type string
-- set_attribute off_n IOB "true" -type string
-- synopsys dc_script_end
  signal D_n, q_n, q_p : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDSE port map (D => D, CE => CE, C => C, S => S, Q => q_p);
  off_n : FDRE port map (D => D_n, CE => CE, C => C, R => S, Q => q_n);
  pad_p : OBUF_LVPECL port map (I => q_p , O => O);
  pad_n : OBUF_LVPECL port map (I => q_n, O => OB);
end lvpecl_buff0; -- OBUFDS_FDSE_lvpecl

-- **************
-- Output Latches
-- **************

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFDS_LD_LVPECL is
  port (
    D, G : in std_logic;
    O, OB : out std_logic
  );
end entity OBUFDS_LD_LVPECL;

architecture lvpecl_buff0 of OBUFDS_LD_lvpecl is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute olatch_p IOB "true" -type string
-- set_attribute olatch_n IOB "true" -type string
-- synopsys dc_script_end
  signal D_n, q_n, q_p, CLR : std_logic;
begin
  CLR <= '0';
  inv_n : INV port map (I => D, O => D_n);
  olatch_p : LDC port map (D => D, G => G, CLR => CLR, Q => q_p);
  olatch_n : LDP port map (D => D_n, G => G, PRE => CLR, Q => q_n);
  pad_p : OBUF_LVPECL port map (I => q_p , O => O);
  pad_n : OBUF_LVPECL port map (I => q_n, O => OB);
end lvpecl_buff0; -- OBUFDS_LD_lvpecl

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFDS_LDE_LVPECL is
  port (
    D, GE, G : in std_logic;
    O, OB : out std_logic
  );
end entity OBUFDS_LDE_LVPECL;

architecture lvpecl_buff0 of OBUFDS_LDE_lvpecl is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute olatch_p IOB "true" -type string
-- set_attribute olatch_n IOB "true" -type string
-- synopsys dc_script_end
  signal D_n, q_n, q_p, CLR : std_logic;
begin
  CLR <= '0';
  inv_n : INV port map (I => D, O => D_n);
  olatch_p : LDCE port map (D => D, GE => GE, G => G, CLR => CLR, Q => q_p);
  olatch_n : LDPE port map (D => D_n, GE => GE, G => G, PRE => CLR, Q => q_n);
  pad_p : OBUF_LVPECL port map (I => q_p , O => O);
  pad_n : OBUF_LVPECL port map (I => q_n, O => OB);
end lvpecl_buff0; -- OBUFDS_LDE_lvpecl

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFDS_LDC_LVPECL is
  port (
    D, G, CLR : in std_logic;
    O, OB : out std_logic
  );
end entity OBUFDS_LDC_LVPECL;

architecture lvpecl_buff0 of OBUFDS_LDC_lvpecl is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute olatch_p IOB "true" -type string
-- set_attribute olatch_n IOB "true" -type string
-- synopsys dc_script_end
  signal D_n, q_n, q_p : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  olatch_p : LDC port map (D => D, G => G, CLR => CLR, Q => q_p);
  olatch_n : LDP port map (D => D_n, G => G, PRE => CLR, Q => q_n);
  pad_p : OBUF_LVPECL port map (I => q_p , O => O);