io_lvds_synplify.vhd

基于VHDL语言的低压差分接口规范的实现

    D, T, C, CLR : in std_logic;
    O, OB : out std_logic
  );
  attribute syn_preserve of O, OB : signal is true;
end entity OBUFTDS_FDC_LVDS;

architecture lvds_buff0 of OBUFTDS_FDC_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of inv_n: label is true;
  attribute syn_noprune of off_p: label is true;
  attribute xc_ioff     of off_p: label is true;
  attribute syn_noprune of off_n: label is true;
  attribute xc_ioff     of off_n: label is true;
  attribute syn_noprune of tri_p: label is true;
  attribute xc_ioff     of tri_p: label is true;
  attribute syn_noprune of tri_n: label is true;
  attribute xc_ioff     of tri_n: label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal D_n, q_n, q_p, t_p, t_n : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDC port map (D => D, C => C, CLR => CLR, Q => q_p);
  off_n : FDP port map (D => D_n, C => C, PRE => CLR, Q => q_n);
  tri_p : FDP port map (D => T, C => C, PRE => CLR, Q => t_p);
  tri_n : FDP port map (D => T, C => C, PRE => CLR, Q => t_n);
  pad_p : OBUFT_LVDS port map (I => q_p, T => t_p, O => O);
  pad_n : OBUFT_LVDS port map (I => q_n, T => t_n, O => OB);
end lvds_buff0; -- OBUFTDS_FDC_LVDS

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFTDS_FDCE_LVDS is
  port (
    D, T, CE, C, CLR : in std_logic;
    O, OB : out std_logic
  );
  attribute syn_preserve of O, OB : signal is true;
end entity OBUFTDS_FDCE_LVDS;

architecture lvds_buff0 of OBUFTDS_FDCE_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of inv_n: label is true;
  attribute syn_noprune of off_p: label is true;
  attribute xc_ioff     of off_p: label is true;
  attribute syn_noprune of off_n: label is true;
  attribute xc_ioff     of off_n: label is true;
  attribute syn_noprune of tri_p: label is true;
  attribute xc_ioff     of tri_p: label is true;
  attribute syn_noprune of tri_n: label is true;
  attribute xc_ioff     of tri_n: label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal D_n, q_n, q_p, t_p, t_n : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDCE port map (D => D, CE => CE, C => C, CLR => CLR, Q => q_p);
  off_n : FDPE port map (D => D_n, CE => CE, C => C, PRE => CLR, Q => q_n);
  tri_p : FDPE port map (D => T, CE => CE, C => C, PRE => CLR, Q => t_p);
  tri_n : FDPE port map (D => T, CE => CE, C => C, PRE => CLR, Q => t_n);
  pad_p : OBUFT_LVDS port map (I => q_p, T => t_p, O => O);
  pad_n : OBUFT_LVDS port map (I => q_n, T => t_n, O => OB);
end lvds_buff0; -- OBUFTDS_FDCE_LVDS

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFTDS_FDP_LVDS is
  port (
    D, T, C, PRE : in std_logic;
    O, OB : out std_logic
  );
  attribute syn_preserve of O, OB : signal is true; 
end entity OBUFTDS_FDP_LVDS;

architecture lvds_buff0 of OBUFTDS_FDP_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of inv_n: label is true;
  attribute syn_noprune of off_p: label is true;
  attribute xc_ioff     of off_p: label is true;
  attribute syn_noprune of off_n: label is true;
  attribute xc_ioff     of off_n: label is true;
  attribute syn_noprune of tri_p: label is true;
  attribute xc_ioff     of tri_p: label is true;
  attribute syn_noprune of tri_n: label is true;
  attribute xc_ioff     of tri_n: label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal D_n, q_n, q_p, t_p, t_n : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDP port map (D => D, C => C, PRE => PRE, Q => q_p);
  off_n : FDC port map (D => D_n, C => C, CLR => PRE, Q => q_n);
  tri_p : FDP port map (D => T, C => C, PRE => PRE, Q => t_p);
  tri_n : FDP port map (D => T, C => C, PRE => PRE, Q => t_n);
  pad_p : OBUFT_LVDS port map (I => q_p, T => t_p, O => O);
  pad_n : OBUFT_LVDS port map (I => q_n, T => t_n, O => OB);
end lvds_buff0; -- OBUFTDS_FDP_LVDS

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFTDS_FDPE_LVDS is
  port (
    D, T, CE, C, PRE : in std_logic;
    O, OB : out std_logic
  );
  attribute syn_preserve of O, OB : signal is true;
end entity OBUFTDS_FDPE_LVDS;

architecture lvds_buff0 of OBUFTDS_FDPE_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of inv_n: label is true;
  attribute syn_noprune of off_p: label is true;
  attribute xc_ioff     of off_p: label is true;
  attribute syn_noprune of off_n: label is true;
  attribute xc_ioff     of off_n: label is true;
  attribute syn_noprune of tri_p: label is true;
  attribute xc_ioff     of tri_p: label is true;
  attribute syn_noprune of tri_n: label is true;
  attribute xc_ioff     of tri_n: label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal D_n, q_n, q_p, t_p, t_n : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDPE port map (D => D, CE => CE, C => C, PRE => PRE, Q => q_p);
  off_n : FDCE port map (D => D_n, CE => CE, C => C, CLR => PRE, Q => q_n);
  tri_p : FDPE port map (D => T, CE => CE, C => C, PRE => PRE, Q => t_p);
  tri_n : FDPE port map (D => T, CE => CE, C => C, PRE => PRE, Q => t_n);
  pad_p : OBUFT_LVDS port map (I => q_p, T => t_p, O => O);
  pad_n : OBUFT_LVDS port map (I => q_n, T => t_n, O => OB);
end lvds_buff0; -- OBUFTDS_FDPE_LVDS

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFTDS_FDR_LVDS is
  port (
    D, T, C, R : in std_logic;
    O, OB : out std_logic
  );
  attribute syn_preserve of O, OB : signal is true;
end entity OBUFTDS_FDR_LVDS;

architecture lvds_buff0 of OBUFTDS_FDR_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of inv_n: label is true;
  attribute syn_noprune of off_p: label is true;
  attribute xc_ioff     of off_p: label is true;
  attribute syn_noprune of off_n: label is true;
  attribute xc_ioff     of off_n: label is true;
  attribute syn_noprune of tri_p: label is true;
  attribute xc_ioff     of tri_p: label is true;
  attribute syn_noprune of tri_n: label is true;
  attribute xc_ioff     of tri_n: label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal D_n, q_n, q_p, t_p, t_n : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDR port map (D => D, C => C, R => R, Q => q_p);
  off_n : FDS port map (D => D_n, C => C, S => R, Q => q_n);
  tri_p : FDS port map (D => T, C => C, S => R, Q => t_p);
  tri_n : FDS port map (D => T, C => C, S => R, Q => t_n);
  pad_p : OBUFT_LVDS port map (I => q_p, T => t_p, O => O);
  pad_n : OBUFT_LVDS port map (I => q_n, T => t_n, O => OB);
end lvds_buff0; -- OBUFTDS_FDR_LVDS

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFTDS_FDRE_LVDS is
  port (
    D, T, CE, C, R : in std_logic;
    O, OB : out std_logic
  );
  attribute syn_preserve of O, OB : signal is true;
end entity OBUFTDS_FDRE_LVDS;

architecture lvds_buff0 of OBUFTDS_FDRE_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of inv_n: label is true;
  attribute syn_noprune of off_p: label is true;
  attribute xc_ioff     of off_p: label is true;
  attribute syn_noprune of off_n: label is true;
  attribute xc_ioff     of off_n: label is true;
  attribute syn_noprune of tri_p: label is true;
  attribute xc_ioff     of tri_p: label is true;
  attribute syn_noprune of tri_n: label is true;
  attribute xc_ioff     of tri_n: label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal D_n, q_n, q_p, t_p, t_n : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDRE port map (D => D, CE => CE, C => C, R => R, Q => q_p);
  off_n : FDSE port map (D => D_n, CE => CE, C => C, S => R, Q => q_n);
  tri_p : FDSE port map (D => T, CE => CE, C => C, S => R, Q => t_p);
  tri_n : FDSE port map (D => T, CE => CE, C => C, S => R, Q => t_n);
  pad_p : OBUFT_LVDS port map (I => q_p, T => t_p, O => O);
  pad_n : OBUFT_LVDS port map (I => q_n, T => t_n, O => OB);
end lvds_buff0; -- OBUFTDS_FDRE_LVDS

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFTDS_FDS_LVDS is
  port (
    D, T, C, S : in std_logic;
    O, OB : out std_logic
  );
  attribute syn_preserve of O, OB : signal is true;
end entity OBUFTDS_FDS_LVDS;

architecture lvds_buff0 of OBUFTDS_FDS_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of inv_n: label is true;
  attribute syn_noprune of off_p: label is true;
  attribute xc_ioff     of off_p: label is true;
  attribute syn_noprune of off_n: label is true;
  attribute xc_ioff     of off_n: label is true;
  attribute syn_noprune of tri_p: label is true;
  attribute xc_ioff     of tri_p: label is true;
  attribute syn_noprune of tri_n: label is true;
  attribute xc_ioff     of tri_n: label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal D_n, q_n, q_p, t_p, t_n : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDS port map (D => D, C => C, S => S, Q => q_p);
  off_n : FDR port map (D => D_n, C => C, R => S, Q => q_n);
  tri_p : FDS port map (D => T, C => C, S => S, Q => t_p);
  tri_n : FDS port map (D => T, C => C, S => S, Q => t_n);
  pad_p : OBUFT_LVDS port map (I => q_p, T => t_p, O => O);
  pad_n : OBUFT_LVDS port map (I => q_n, T => t_n, O => OB);
end lvds_buff0; -- OBUFTDS_FDS_LVDS

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFTDS_FDSE_LVDS is
  port (
    D, T, CE, C, S : in std_logic;
    O, OB : out std_logic
  );
  attribute syn_preserve of O, OB : signal is true;
end entity OBUFTDS_FDSE_LVDS;

architecture lvds_buff0 of OBUFTDS_FDSE_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of inv_n: label is true;
  attribute syn_noprune of off_p: label is true;
  attribute xc_ioff     of off_p: label is true;
  attribute syn_noprune of off_n: label is true;
  attribute xc_ioff     of off_n: label is true;
  attribute syn_noprune of tri_p: label is true;
  attribute xc_ioff     of tri_p: label is true;
  attribute syn_noprune of tri_n: label is true;
  attribute xc_ioff     of tri_n: label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal D_n, q_n, q_p, t_p, t_n : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDSE port map (D => D, CE => CE, C => C, S => S, Q => q_p);
  off_n : FDRE port map (D => D_n, CE => CE, C => C, R => S, Q => q_n);
  tri_p : FDSE port map (D => T, CE => CE, C => C, S => S, Q => t_p);
  tri_n : FDSE port map (D => T, CE => CE, C => C, S => S, Q => t_n);
  pad_p : OBUFT_LVDS port map (I => q_p, T => t_p, O => O);
  pad_n : OBUFT_LVDS port map (I => q_n, T => t_n, O => OB);
end lvds_buff0; -- OBUFTDS_FDSE_LVDS

-- ************************
-- Tri-state output latches
-- ************************

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFTDS_LD_LVDS is
  port (
    D, T, G : in std_logic;
    O, OB : out std_logic
  );
  attribute syn_preserve of O, OB : signal is true;
end entity OBUFTDS_LD_LVDS;

architecture lvds_buff0 of OBUFTDS_LD_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of inv_n: label is true;
  attribute syn_noprune of olatch_p: label is true;
  attribute xc_ioff     of olatch_p: label is true;
  attribute syn_noprune of olatch_n: label is true;
  attribute xc_ioff     of olatch_n: label is true;
  attribute syn_noprune of tri_p: label is true;
  attribute xc_ioff     of tri_p: label is true;
  attribute syn_noprune of tri_n: label is true;
  attribute xc_ioff     of tri_n: label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal D_n, q_n, q_p, t_p, t_n, CLR : std_logic;
begin
  CLR <= '0';
  inv_n : INV port map (I => D, O => D_n);
  olatch_p : LDC port map (D => D, G => G, CLR => CLR, Q => q_p);
  olatch_n : LDP port map (D => D_n, G => G, PRE => CLR, Q => q_n);
  tri_p : LDP port map (D => T, G => G, PRE => CLR, Q => t_p);
  tri_n : LDP port map (D => T, G => G, PRE => CLR, Q => t_n);
  pad_p : OBUFT_LVDS port map (I => q_p, T => t_p, O => O);
  pad_n : OBUFT_LVDS port map (I => q_n, T => t_n, O => OB);
end lvds_buff0; -- OBUFTDS_LD_LVDS

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFTDS_LDE_LVDS is
  port (
    D, T, GE, G : in std_logic;
    O, OB : out std_logic
  );
  attribute syn_preserve of O, OB : signal is true;
end entity OBUFTDS_LDE_LVDS;

architecture lvds_buff0 of OBUFTDS_LDE_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;