io_lvds_synplify.vhd

基于VHDL语言的低压差分接口规范的实现

use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFDS_FDS_LVDS is
  port (
    D, C, S : in std_logic;
    O, OB : out std_logic
  );
  attribute syn_preserve of O, OB : signal is true;
end entity OBUFDS_FDS_LVDS;

architecture lvds_buff0 of OBUFDS_FDS_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of inv_n: label is true;
  attribute syn_noprune of off_p: label is true;
  attribute xc_ioff     of off_p: label is true;
  attribute syn_noprune of off_n: label is true;
  attribute xc_ioff     of off_n: label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal D_n, q_n, q_p : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDS port map (D => D, C => C, S => S, Q => q_p);
  off_n : FDR port map (D => D_n, C => C, R => S, Q => q_n);
  pad_p : OBUF_LVDS port map (I => q_p , O => O);
  pad_n : OBUF_LVDS port map (I => q_n, O => OB);
end lvds_buff0; -- OBUFDS_FDS_LVDS

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFDS_FDSE_LVDS is
  port (
    D, CE, C, S : in std_logic;
    O, OB : out std_logic
  );
  attribute syn_preserve of O, OB : signal is true;
end entity OBUFDS_FDSE_LVDS;

architecture lvds_buff0 of OBUFDS_FDSE_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of inv_n: label is true;
  attribute syn_noprune of off_p: label is true;
  attribute xc_ioff     of off_p: label is true;
  attribute syn_noprune of off_n: label is true;
  attribute xc_ioff     of off_n: label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal D_n, q_n, q_p : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDSE port map (D => D, CE => CE, C => C, S => S, Q => q_p);
  off_n : FDRE port map (D => D_n, CE => CE, C => C, R => S, Q => q_n);
  pad_p : OBUF_LVDS port map (I => q_p , O => O);
  pad_n : OBUF_LVDS port map (I => q_n, O => OB);
end lvds_buff0; -- OBUFDS_FDSE_LVDS

-- **************
-- Output Latches
-- **************

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFDS_LD_LVDS is
  port (
    D, G : in std_logic;
    O, OB : out std_logic
  );
  attribute syn_preserve of O, OB : signal is true;
end entity OBUFDS_LD_LVDS;

architecture lvds_buff0 of OBUFDS_LD_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of inv_n: label is true;
  attribute syn_noprune of olatch_p: label is true;
  attribute xc_ioff     of olatch_p: label is true;
  attribute syn_noprune of olatch_n: label is true;
  attribute xc_ioff     of olatch_n: label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal D_n, q_n, q_p, CLR : std_logic;
begin
  CLR <= '0';
  inv_n : INV port map (I => D, O => D_n);
  olatch_p : LDC port map (D => D, G => G, CLR => CLR, Q => q_p);
  olatch_n : LDP port map (D => D_n, G => G, PRE => CLR, Q => q_n);
  pad_p : OBUF_LVDS port map (I => q_p , O => O);
  pad_n : OBUF_LVDS port map (I => q_n, O => OB);
end lvds_buff0; -- OBUFDS_LD_LVDS

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFDS_LDE_LVDS is
  port (
    D, GE, G : in std_logic;
    O, OB : out std_logic
  );
  attribute syn_preserve of O, OB : signal is true;
end entity OBUFDS_LDE_LVDS;

architecture lvds_buff0 of OBUFDS_LDE_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of inv_n: label is true;
  attribute syn_noprune of olatch_p: label is true;
  attribute xc_ioff     of olatch_p: label is true;
  attribute syn_noprune of olatch_n: label is true;
  attribute xc_ioff     of olatch_n: label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal D_n, q_n, q_p, CLR : std_logic;
begin
  CLR <= '0';
  inv_n : INV port map (I => D, O => D_n);
  olatch_p : LDCE port map (D => D, GE => GE, G => G, CLR => CLR, Q => q_p);
  olatch_n : LDPE port map (D => D_n, GE => GE, G => G, PRE => CLR, Q => q_n);
  pad_p : OBUF_LVDS port map (I => q_p , O => O);
  pad_n : OBUF_LVDS port map (I => q_n, O => OB);
end lvds_buff0; -- OBUFDS_LDE_LVDS

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFDS_LDC_LVDS is
  port (
    D, G, CLR : in std_logic;
    O, OB : out std_logic
  );
  attribute syn_preserve of O, OB : signal is true;
end entity OBUFDS_LDC_LVDS;

architecture lvds_buff0 of OBUFDS_LDC_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of inv_n: label is true;
  attribute syn_noprune of olatch_p: label is true;
  attribute xc_ioff     of olatch_p: label is true;
  attribute syn_noprune of olatch_n: label is true;
  attribute xc_ioff     of olatch_n: label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal D_n, q_n, q_p : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  olatch_p : LDC port map (D => D, G => G, CLR => CLR, Q => q_p);
  olatch_n : LDP port map (D => D_n, G => G, PRE => CLR, Q => q_n);
  pad_p : OBUF_LVDS port map (I => q_p , O => O);
  pad_n : OBUF_LVDS port map (I => q_n, O => OB);
end lvds_buff0; -- OBUFDS_LDC_LVDS

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFDS_LDCE_LVDS is
  port (
    D, GE, G, CLR : in std_logic;
    O, OB : out std_logic
  );
  attribute syn_preserve of O, OB : signal is true;
end entity OBUFDS_LDCE_LVDS;

architecture lvds_buff0 of OBUFDS_LDCE_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of inv_n: label is true;
  attribute syn_noprune of olatch_p: label is true;
  attribute xc_ioff     of olatch_p: label is true;
  attribute syn_noprune of olatch_n: label is true;
  attribute xc_ioff     of olatch_n: label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal D_n, q_n, q_p : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  olatch_p : LDCE port map (D => D, GE => GE, G => G, CLR => CLR, Q => q_p);
  olatch_n : LDPE port map (D => D_n, GE => GE, G => G, PRE => CLR, Q => q_n);
  pad_p : OBUF_LVDS port map (I => q_p , O => O);
  pad_n : OBUF_LVDS port map (I => q_n, O => OB);
end lvds_buff0; -- OBUFDS_LDCE_LVDS

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFDS_LDP_LVDS is
  port (
    D, G, PRE : in std_logic;
    O, OB : out std_logic
  );
  attribute syn_preserve of O, OB : signal is true;
end entity OBUFDS_LDP_LVDS;

architecture lvds_buff0 of OBUFDS_LDP_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of inv_n: label is true;
  attribute syn_noprune of olatch_p: label is true;
  attribute xc_ioff     of olatch_p: label is true;
  attribute syn_noprune of olatch_n: label is true;
  attribute xc_ioff     of olatch_n: label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal D_n, q_n, q_p : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  olatch_p : LDP port map (D => D, G => G, PRE => PRE, Q => q_p);
  olatch_n : LDC port map (D => D_n, G => G, CLR => PRE, Q => q_n);
  pad_p : OBUF_LVDS port map (I => q_p , O => O);
  pad_n : OBUF_LVDS port map (I => q_n, O => OB);
end lvds_buff0; -- OBUFDS_LDP_LVDS

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFDS_LDPE_LVDS is
  port (
    D, GE, G, PRE : in std_logic;
    O, OB : out std_logic
  );
  attribute syn_preserve of O, OB : signal is true;
end entity OBUFDS_LDPE_LVDS;

architecture lvds_buff0 of OBUFDS_LDPE_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of inv_n: label is true;
  attribute syn_noprune of olatch_p: label is true;
  attribute xc_ioff     of olatch_p: label is true;
  attribute syn_noprune of olatch_n: label is true;
  attribute xc_ioff     of olatch_n: label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal D_n, q_n, q_p : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  olatch_p : LDPE port map (D => D, GE => GE, G => G, PRE => PRE, Q => q_p);
  olatch_n : LDCE port map (D => D_n, GE => GE, G => G, CLR => PRE, Q => q_n);
  pad_p : OBUF_LVDS port map (I => q_p , O => O);
  pad_n : OBUF_LVDS port map (I => q_n, O => OB);
end lvds_buff0; -- OBUFDS_LDPE_LVDS


-- *************************************
-- Start of the Tri-State Output Buffers
-- Tri-state output flipflops
-- *************************************

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFTDS_FD_LVDS is
  port (
    D, T, C : in std_logic;
    O, OB : out std_logic
  );
  attribute syn_preserve of O, OB : signal is true;
end entity OBUFTDS_FD_LVDS;

architecture lvds_buff0 of OBUFTDS_FD_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of inv_n: label is true;
  attribute syn_noprune of off_p: label is true;
  attribute xc_ioff     of off_p: label is true;
  attribute syn_noprune of off_n: label is true;
  attribute xc_ioff     of off_n: label is true;
  attribute syn_noprune of tri_p: label is true;
  attribute xc_ioff     of tri_p: label is true;
  attribute syn_noprune of tri_n: label is true;
  attribute xc_ioff     of tri_n: label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal D_n, q_n, q_p, t_p, t_n, CLR : std_logic;
begin
  CLR <= '0';
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDC port map (D => D, C => C, CLR => CLR, Q => q_p);
  off_n : FDP port map (D => D_n, C => C, PRE => CLR, Q => q_n);
  tri_p : FDP port map (D => T, C => C, PRE => CLR, Q => t_p);
  tri_n : FDP port map (D => T, C => C, PRE => CLR, Q => t_n);
  pad_p : OBUFT_LVDS port map (I => q_p, T => t_p, O => O);
  pad_n : OBUFT_LVDS port map (I => q_n, T => t_n, O => OB);
end lvds_buff0; -- OBUFTDS_FD_LVDS

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFTDS_FDE_LVDS is
  port (
    D, T, CE, C : in std_logic;
    O, OB : out std_logic
  );
  attribute syn_preserve of O, OB : signal is true;
end entity OBUFTDS_FDE_LVDS;

architecture lvds_buff0 of OBUFTDS_FDE_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of inv_n: label is true;
  attribute syn_noprune of off_p: label is true;
  attribute xc_ioff     of off_p: label is true;
  attribute syn_noprune of off_n: label is true;
  attribute xc_ioff     of off_n: label is true;
  attribute syn_noprune of tri_p: label is true;
  attribute xc_ioff     of tri_p: label is true;
  attribute syn_noprune of tri_n: label is true;
  attribute xc_ioff     of tri_n: label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal D_n, q_n, q_p, t_p, t_n, CLR : std_logic;
begin
  CLR <= '0';
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDCE port map (D => D, CE => CE, C => C, CLR => CLR, Q => q_p);
  off_n : FDPE port map (D => D_n, CE => CE, C => C, PRE => CLR, Q => q_n);
  tri_p : FDPE port map (D => T, CE => CE, C => C, PRE => CLR, Q => t_p);
  tri_n : FDPE port map (D => T, CE => CE, C => C, PRE => CLR, Q => t_n);
  pad_p : OBUFT_LVDS port map (I => q_p, T => t_p, O => O);
  pad_n : OBUFT_LVDS port map (I => q_n, T => t_n, O => OB);
end lvds_buff0; -- OBUFTDS_FDE_LVDS

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFTDS_FDC_LVDS is
  port (