io_lvds_synplify.vhd

基于VHDL语言的低压差分接口规范的实现

  attribute syn_noprune of pad_n: label is true;
  signal I_w, IB_w : std_logic;
begin
  ilatch_p : LDC port map (D => I_w, G => G, CLR => CLR, Q => Q);
  pad_p : IBUF_LVDS port map (I => I, O => I_w);
  pad_n : IBUF_LVDS port map (I => IB, O => IB_w);
end lvds_buff0; -- IBUFDS_LDC_LVDS

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity IBUFDS_LDCE_LVDS is
  port (
    I, IB, GE, G, CLR : in std_logic;
    Q : out std_logic
  );
  attribute syn_preserve of Q : signal is true;
end entity IBUFDS_LDCE_LVDS;

architecture lvds_buff0 of IBUFDS_LDCE_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of ilatch_p : label is true;
  attribute xc_ioff     of ilatch_p : label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal I_w, IB_w : std_logic;
begin
  ilatch_p : LDCE port map (D => I_w, GE => GE, G => G, CLR => CLR, Q => Q);
  pad_p : IBUF_LVDS port map (I => I, O => I_w);
  pad_n : IBUF_LVDS port map (I => IB, O => IB_w);
end lvds_buff0; -- IBUFDS_LDCE_LVDS

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity IBUFDS_LDP_LVDS is
  port (
    I, IB, G, PRE : in std_logic;
    Q : out std_logic
  );
  attribute syn_preserve of Q : signal is true;
end entity IBUFDS_LDP_LVDS;

architecture lvds_buff0 of IBUFDS_LDP_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of ilatch_p : label is true;
  attribute xc_ioff     of ilatch_p : label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal I_w, IB_w : std_logic;
begin
  ilatch_p : LDP port map (D => I_w, G => G, PRE => PRE, Q => Q);
  pad_p : IBUF_LVDS port map (I => I, O => I_w);
  pad_n : IBUF_LVDS port map (I => IB, O => IB_w);
end lvds_buff0; -- IBUFDS_LDP_LVDS

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity IBUFDS_LDPE_LVDS is
  port (
    I, IB, GE, G, PRE : in std_logic;
    Q : out std_logic
  );
  attribute syn_preserve of Q : signal is true;
end entity IBUFDS_LDPE_LVDS;

architecture lvds_buff0 of IBUFDS_LDPE_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of ilatch_p : label is true;
  attribute xc_ioff     of ilatch_p : label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal I_w, IB_w : std_logic;
begin
  ilatch_p : LDPE port map (D => I_w, GE => GE, G => G, PRE => PRE, Q => Q);
  pad_p : IBUF_LVDS port map (I => I, O => I_w);
  pad_n : IBUF_LVDS port map (I => IB, O => IB_w);
end lvds_buff0; -- IBUFDS_LDPE_LVDS

-- ***************************
-- Start of the Output Buffers
-- Output Flipflops
-- ***************************

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFDS_FD_LVDS is
  port (
    D, C : in std_logic;
    O, OB : out std_logic
  );
  attribute syn_preserve of O, OB : signal is true;
end entity OBUFDS_FD_LVDS;

architecture lvds_buff0 of OBUFDS_FD_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of inv_n: label is true;
  attribute syn_noprune of off_p: label is true;
  attribute xc_ioff     of off_p: label is true;
  attribute syn_noprune of off_n: label is true;
  attribute xc_ioff     of off_n: label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal D_n, q_n, q_p, CLR : std_logic;
begin
  CLR <= '0';
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDC port map (D => D, C => C, CLR => CLR, Q => q_p);
  off_n : FDP port map (D => D_n, C => C, PRE => CLR, Q => q_n);
  pad_p : OBUF_LVDS port map (I => q_p , O => O);
  pad_n : OBUF_LVDS port map (I => q_n, O => OB);
end lvds_buff0; -- OBUFDS_FD_LVDS

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFDS_FDE_LVDS is
  port (
    D, CE, C : in std_logic;
    O, OB : out std_logic
  );
  attribute syn_preserve of O, OB : signal is true;
end entity OBUFDS_FDE_LVDS;

architecture lvds_buff0 of OBUFDS_FDE_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of inv_n: label is true;
  attribute syn_noprune of off_p: label is true;
  attribute xc_ioff     of off_p: label is true;
  attribute syn_noprune of off_n: label is true;
  attribute xc_ioff     of off_n: label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal D_n, q_n, q_p, CLR : std_logic;
begin
  CLR <= '0';
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDCE port map (D => D, CE => CE, C => C, CLR => CLR, Q => q_p);
  off_n : FDPE port map (D => D_n, CE => CE, C => C, PRE => CLR, Q => q_n);
  pad_p : OBUF_LVDS port map (I => q_p , O => O);
  pad_n : OBUF_LVDS port map (I => q_n, O => OB);
end lvds_buff0; -- OBUFDS_FDE_LVDS

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFDS_FDC_LVDS is
  port (
    D, C, CLR : in std_logic;
    O, OB : out std_logic
  );
  attribute syn_preserve of O, OB : signal is true;
end entity OBUFDS_FDC_LVDS;

architecture lvds_buff0 of OBUFDS_FDC_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of inv_n: label is true;
  attribute syn_noprune of off_p: label is true;
  attribute xc_ioff     of off_p: label is true;
  attribute syn_noprune of off_n: label is true;
  attribute xc_ioff     of off_n: label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal D_n, q_n, q_p : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDC port map (D => D, C => C, CLR => CLR, Q => q_p);
  off_n : FDP port map (D => D_n, C => C, PRE => CLR, Q => q_n);
  pad_p : OBUF_LVDS port map (I => q_p , O => O);
  pad_n : OBUF_LVDS port map (I => q_n, O => OB);
end lvds_buff0; -- OBUFDS_FDC_LVDS

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFDS_FDCE_LVDS is
  port (
    D, CE, C, CLR : in std_logic;
    O, OB : out std_logic
  );
  attribute syn_preserve of O, OB : signal is true;
end entity OBUFDS_FDCE_LVDS;

architecture lvds_buff0 of OBUFDS_FDCE_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of inv_n: label is true;
  attribute syn_noprune of off_p: label is true;
  attribute xc_ioff     of off_p: label is true;
  attribute syn_noprune of off_n: label is true;
  attribute xc_ioff     of off_n: label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal D_n, q_n, q_p : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDCE port map (D => D, CE => CE, C => C, CLR => CLR, Q => q_p);
  off_n : FDPE port map (D => D_n, CE => CE, C => C, PRE => CLR, Q => q_n);
  pad_p : OBUF_LVDS port map (I => q_p , O => O);
  pad_n : OBUF_LVDS port map (I => q_n, O => OB);
end lvds_buff0; -- OBUFDS_FDCE_LVDS

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFDS_FDP_LVDS is
  port (
    D, C, PRE : in std_logic;
    O, OB : out std_logic
  );
  attribute syn_preserve of O, OB : signal is true;
end entity OBUFDS_FDP_LVDS;

architecture lvds_buff0 of OBUFDS_FDP_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of inv_n: label is true;
  attribute syn_noprune of off_p: label is true;
  attribute xc_ioff     of off_p: label is true;
  attribute syn_noprune of off_n: label is true;
  attribute xc_ioff     of off_n: label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal D_n, q_n, q_p : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDP port map (D => D, C => C, PRE => PRE, Q => q_p);
  off_n : FDC port map (D => D_n, C => C, CLR => PRE, Q => q_n);
  pad_p : OBUF_LVDS port map (I => q_p , O => O);
  pad_n : OBUF_LVDS port map (I => q_n, O => OB);
end lvds_buff0; -- OBUFDS_FDP_LVDS

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFDS_FDPE_LVDS is
  port (
    D, CE, C, PRE : in std_logic;
    O, OB : out std_logic
  );
  attribute syn_preserve of O, OB : signal is true;
end entity OBUFDS_FDPE_LVDS;

architecture lvds_buff0 of OBUFDS_FDPE_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of inv_n: label is true;
  attribute syn_noprune of off_p: label is true;
  attribute xc_ioff     of off_p: label is true;
  attribute syn_noprune of off_n: label is true;
  attribute xc_ioff     of off_n: label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal D_n, q_n, q_p : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDPE port map (D => D, CE => CE, C => C, PRE => PRE, Q => q_p);
  off_n : FDCE port map (D => D_n, CE => CE, C => C, CLR => PRE, Q => q_n);
  pad_p : OBUF_LVDS port map (I => q_p , O => O);
  pad_n : OBUF_LVDS port map (I => q_n, O => OB);
end lvds_buff0; -- OBUFDS_FDPE_LVDS

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFDS_FDR_LVDS is
  port (
    D, C, R : in std_logic;
    O, OB : out std_logic
  );
  attribute syn_preserve of O, OB : signal is true;
end entity OBUFDS_FDR_LVDS;

architecture lvds_buff0 of OBUFDS_FDR_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of inv_n: label is true;
  attribute syn_noprune of off_p: label is true;
  attribute xc_ioff     of off_p: label is true;
  attribute syn_noprune of off_n: label is true;
  attribute xc_ioff     of off_n: label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal D_n, q_n, q_p : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDR port map (D => D, C => C, R => R, Q => q_p);
  off_n : FDS port map (D => D_n, C => C, S => R, Q => q_n);
  pad_p : OBUF_LVDS port map (I => q_p , O => O);
  pad_n : OBUF_LVDS port map (I => q_n, O => OB);
end lvds_buff0; -- OBUFDS_FDR_LVDS

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity OBUFDS_FDRE_LVDS is
  port (
    D, CE, C, R : in std_logic;
    O, OB : out std_logic
  );
  attribute syn_preserve of O, OB : signal is true;
end entity OBUFDS_FDRE_LVDS;

architecture lvds_buff0 of OBUFDS_FDRE_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of inv_n: label is true;
  attribute syn_noprune of off_p: label is true;
  attribute xc_ioff     of off_p: label is true;
  attribute syn_noprune of off_n: label is true;
  attribute xc_ioff     of off_n: label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal D_n, q_n, q_p : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDRE port map (D => D, CE => CE, C => C, R => R, Q => q_p);
  off_n : FDSE port map (D => D_n, CE => CE, C => C, S => R, Q => q_n);
  pad_p : OBUF_LVDS port map (I => q_p , O => O);
  pad_n : OBUF_LVDS port map (I => q_n, O => OB);
end lvds_buff0; -- OBUFDS_FDRE_LVDS

library ieee;