io_lvds_synplify.vhd

基于VHDL语言的低压差分接口规范的实现

-- **************************
-- Start of the Input Buffers
-- Input Flip Flops  
-- **************************

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity IBUFDS_FD_LVDS is
  port (
    I, IB, C : in std_logic;
    Q : out std_logic
  );
  attribute syn_preserve of Q : signal is true;
end entity IBUFDS_FD_LVDS;

architecture lvds_buff0 of IBUFDS_FD_LVDS is
  signal I_w, IB_w : std_logic;
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of iff_p: label is true;
  attribute xc_ioff     of iff_p : label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
begin
  iff_p : FD port map (D => I_w, C => C, Q => Q);
  pad_p : IBUF_LVDS port map (I => I, O => I_w);   
  pad_n : IBUF_LVDS port map (I => IB, O => IB_w); 
end lvds_buff0; -- IBUFDS_FD_LVDS

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity IBUFDS_FDE_LVDS is
  port (
    I, IB, CE, C : in std_logic;
    Q : out std_logic
  );
  attribute syn_preserve of Q : signal is true;
end entity IBUFDS_FDE_LVDS;

architecture lvds_buff0 of IBUFDS_FDE_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of iff_p: label is true;
  attribute xc_ioff     of iff_p : label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal I_w, IB_w : std_logic;
begin
  iff_p : FDE port map (D => I_w, CE => CE, C => C, Q => Q);
  pad_p : IBUF_LVDS port map (I => I, O => I_w);
  pad_n : IBUF_LVDS port map (I => IB, O => IB_w);
end lvds_buff0; -- IBUFDS_FDE_LVDS

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity IBUFDS_FDC_LVDS is
  port (
    I, IB, C, CLR : in std_logic;
    Q : out std_logic
  );
  attribute syn_preserve of Q : signal is true;
end entity IBUFDS_FDC_LVDS;

architecture lvds_buff0 of IBUFDS_FDC_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of iff_p: label is true;
  attribute xc_ioff     of iff_p : label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal I_w, IB_w : std_logic;
begin
  iff_p : FDC port map (D => I_w, C => C, CLR => CLR, Q => Q);
  pad_p : IBUF_LVDS port map (I => I, O => I_w);
  pad_n : IBUF_LVDS port map (I => IB, O => IB_w);
end lvds_buff0; -- IBUFDS_FDC_LVDS

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity IBUFDS_FDCE_LVDS is
  port (
    I, IB, CE, C, CLR : in std_logic;
    Q : out std_logic
  );
  attribute syn_preserve of Q : signal is true;
end entity IBUFDS_FDCE_LVDS;

architecture lvds_buff0 of IBUFDS_FDCE_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of iff_p: label is true;
  attribute xc_ioff     of iff_p : label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal I_w, IB_w : std_logic;
begin
  iff_p : FDCE port map (D => I_w, CE => CE, C => C, CLR => CLR, Q => Q);
  pad_p : IBUF_LVDS port map (I => I, O => I_w);
  pad_n : IBUF_LVDS port map (I => IB, O => IB_w);
end lvds_buff0; -- IBUFDS_FDCE_LVDS

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity IBUFDS_FDP_LVDS is
  port (
    I, IB, C, PRE : in std_logic;
    Q : out std_logic
  );
  attribute syn_preserve of Q : signal is true;
end entity IBUFDS_FDP_LVDS;

architecture lvds_buff0 of IBUFDS_FDP_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of iff_p: label is true;
  attribute xc_ioff     of iff_p : label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal I_w, IB_w : std_logic;
begin
  iff_p : FDP port map (D => I_w, C => C, PRE => PRE, Q => Q);
  pad_p : IBUF_LVDS port map (I => I, O => I_w);
  pad_n : IBUF_LVDS port map (I => IB, O => IB_w);
end lvds_buff0; -- IBUFDS_FDP_LVDS

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity IBUFDS_FDPE_LVDS is
  port (
    I, IB, CE, C, PRE : in std_logic;
    Q : out std_logic
  );
  attribute syn_preserve of Q : signal is true;
end entity IBUFDS_FDPE_LVDS;

architecture lvds_buff0 of IBUFDS_FDPE_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of iff_p: label is true;
  attribute xc_ioff     of iff_p : label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal I_w, IB_w : std_logic;
begin
  iff_p : FDPE port map (D => I_w, CE => CE, C => C, PRE => PRE, Q => Q);
  pad_p : IBUF_LVDS port map (I => I, O => I_w);
  pad_n : IBUF_LVDS port map (I => IB, O => IB_w);
end lvds_buff0; -- IBUFDS_FDPE_LVDS

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity IBUFDS_FDR_LVDS is
  port (
    I, IB, C, R : in std_logic;
    Q : out std_logic
  );
  attribute syn_preserve of Q : signal is true;
end entity IBUFDS_FDR_LVDS;

architecture lvds_buff0 of IBUFDS_FDR_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of iff_p: label is true;
  attribute xc_ioff     of iff_p : label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal I_w, IB_w : std_logic;
begin
  iff_p : FDR port map (D => I_w, C => C, R => R, Q => Q);
  pad_p : IBUF_LVDS port map (I => I, O => I_w);
  pad_n : IBUF_LVDS port map (I => IB, O => IB_w);
end lvds_buff0; -- IBUFDS_FDR_LVDS

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity IBUFDS_FDRE_LVDS is
  port (
    I, IB, CE, C, R : in std_logic;
    Q : out std_logic
  );
  attribute syn_preserve of Q : signal is true;
end entity IBUFDS_FDRE_LVDS;

architecture lvds_buff0 of IBUFDS_FDRE_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of iff_p: label is true;
  attribute xc_ioff     of iff_p : label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal I_w, IB_w : std_logic;
begin
  iff_p : FDRE port map (D => I_w, CE => CE, C => C, R => R, Q => Q);
  pad_p : IBUF_LVDS port map (I => I, O => I_w);
  pad_n : IBUF_LVDS port map (I => IB, O => IB_w);
end lvds_buff0; -- IBUFDS_FDRE_LVDS

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity IBUFDS_FDS_LVDS is
  port (
    I, IB, C, S : in std_logic;
    Q : out std_logic
  );
  attribute syn_preserve of Q : signal is true;
end entity IBUFDS_FDS_LVDS;

architecture lvds_buff0 of IBUFDS_FDS_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of iff_p: label is true;
  attribute xc_ioff     of iff_p : label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal I_w, IB_w : std_logic;
begin
  iff_p : FDS port map (D => I_w, C => C, S => S, Q => Q);
  pad_p : IBUF_LVDS port map (I => I, O => I_w);
  pad_n : IBUF_LVDS port map (I => IB, O => IB_w);
end lvds_buff0; -- IBUFDS_FDS_LVDS

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity IBUFDS_FDSE_LVDS is
  port (
    I, IB, CE, C, S : in std_logic;
    Q : out std_logic
  );
  attribute syn_preserve of Q : signal is true;
end entity IBUFDS_FDSE_LVDS;

architecture lvds_buff0 of IBUFDS_FDSE_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of iff_p: label is true;
  attribute xc_ioff     of iff_p : label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal I_w, IB_w : std_logic;
begin
  iff_p : FDSE port map (D => I_w, CE => CE, C => C, S => S, Q => Q);
  pad_p : IBUF_LVDS port map (I => I, O => I_w);
  pad_n : IBUF_LVDS port map (I => IB, O => IB_w);
end lvds_buff0; -- IBUFDS_FDSE_LVDS

-- *************
-- Input Latches
-- *************
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity IBUFDS_LD_LVDS is
  port (
    I, IB, G : in std_logic;
    Q : out std_logic
  );
  attribute syn_preserve of Q : signal is true;
end entity IBUFDS_LD_LVDS;

architecture lvds_buff0 of IBUFDS_LD_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of ilatch_p : label is true;
  attribute xc_ioff     of ilatch_p : label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal I_w, IB_w : std_logic;
begin
  ilatch_p : LD port map (D => I_w, G => G, Q => Q);
  pad_p : IBUF_LVDS port map (I => I, O => I_w);
  pad_n : IBUF_LVDS port map (I => IB, O => IB_w);
end lvds_buff0; -- IBUFDS_LD_LVDS

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity IBUFDS_LDE_LVDS is
  port (
    I, IB, GE, G : in std_logic;
    Q : out std_logic
  );
  attribute syn_preserve of Q : signal is true;
end entity IBUFDS_LDE_LVDS;

architecture lvds_buff0 of IBUFDS_LDE_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of ilatch_p : label is true;
  attribute xc_ioff     of ilatch_p : label is true;
  attribute syn_noprune of pad_p: label is true;
  attribute syn_noprune of pad_n: label is true;
  signal I_w, IB_w : std_logic;
begin
  ilatch_p : LDE port map (D => I_w, GE => GE, G => G, Q => Q);
  pad_p : IBUF_LVDS port map (I => I, O => I_w);
  pad_n : IBUF_LVDS port map (I => IB, O => IB_w);
end lvds_buff0; -- IBUFDS_LDE_LVDS

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
library unisim;
use unisim.vcomponents.all;

entity IBUFDS_LDC_LVDS is
  port (
    I, IB, G, CLR : in std_logic;
    Q : out std_logic
  );
  attribute syn_preserve of Q : signal is true;
end entity IBUFDS_LDC_LVDS;

architecture lvds_buff0 of IBUFDS_LDC_LVDS is
  attribute syn_noprune of lvds_buff0 : architecture is true;
  attribute syn_noprune of ilatch_p : label is true;
  attribute xc_ioff     of ilatch_p : label is true;
  attribute syn_noprune of pad_p: label is true;