io_lvds_synplify.v

基于VHDL语言的低压差分接口规范的实现

// **************************
// Start of the Input Buffers
// Input Flip Flops  
// **************************

module IBUFDS_FD_LVDS (I,IB,C,Q);
input I, IB, C;
output Q;

wire I_w, IB_w /* synthesis syn_keep = 1 */ ;

FD off_p (.D(I_w), .C(C), .Q(Q)) /* synthesis syn_noprune = 1 IOB = true */ ;
IBUF_LVDS pad_p (.I(I),  .O(I_w)) /* synthesis syn_noprune = 1 */ ;
IBUF_LVDS pad_n (.I(IB), .O(IB_w)) /* synthesis syn_noprune = 1 */ ;
endmodule // IBUFDS_FD_LVDS

module IBUFDS_FDE_LVDS (I,IB,CE,C,Q);
input I, IB, CE, C;
output Q;

wire I_w, IB_w /* synthesis syn_keep = 1 */ ;

FDE off_p (.D(I_w), .CE(CE), .C(C), .Q(Q)) /* synthesis syn_noprune = 1 IOB = true */ ;
IBUF_LVDS pad_p (.I(I),  .O(I_w)) /* synthesis syn_noprune = 1 */ ;
IBUF_LVDS pad_n (.I(IB), .O(IB_w)) /* synthesis syn_noprune = 1 */ ;

endmodule // IBUFDS_FDE_LVDS 

module IBUFDS_FDC_LVDS (I,IB,C,CLR,Q);
input I, IB, C, CLR;
output Q;

wire I_w, IB_w /* synthesis syn_keep = 1 */ ;

FDC off_p (.D(I_w), .C(C), .CLR(CLR), .Q(Q)) /* synthesis syn_noprune = 1 IOB = true */ ;
IBUF_LVDS pad_p (.I(I),  .O(I_w)) /* synthesis syn_noprune = 1 */ ;
IBUF_LVDS pad_n (.I(IB), .O(IB_w)) /* synthesis syn_noprune = 1 */ ;

endmodule // IBUFDS_FDC_LVDS 

module IBUFDS_FDCE_LVDS (I,IB,CE,C,CLR,Q);
input I, IB, CE, C, CLR;
output Q;

wire I_w, IB_w /* synthesis syn_keep = 1 */ ;

FDCE off_p (.D(I_w), .CE(CE), .C(C), .CLR(CLR), .Q(Q)) /* synthesis syn_noprune = 1 IOB = true */ ;
IBUF_LVDS pad_p (.I(I),  .O(I_w)) /* synthesis syn_noprune = 1 */ ;
IBUF_LVDS pad_n (.I(IB), .O(IB_w)) /* synthesis syn_noprune = 1 */ ;

endmodule // IBUFDS_FDCE_LVDS

module IBUFDS_FDP_LVDS (I,IB,C,PRE,Q);
input I, IB, C, PRE;
output Q;

wire I_w, IB_w /* synthesis syn_keep = 1 */ ;

FDP off_p (.D(I_w), .C(C), .PRE(PRE), .Q(Q)) /* synthesis syn_noprune = 1 IOB = true */ ;
IBUF_LVDS pad_p (.I(I),  .O(I_w)) /* synthesis syn_noprune = 1 */ ;
IBUF_LVDS pad_n (.I(IB), .O(IB_w)) /* synthesis syn_noprune = 1 */ ;

endmodule // IBUFDS_FDP_LVDS

module IBUFDS_FDPE_LVDS (I,IB,CE,C,PRE,Q);
input I, IB, CE, C, PRE;
output Q;

wire I_w, IB_w /* synthesis syn_keep = 1 */ ;

FDPE off_p (.D(I_w),   .CE(CE), .C(C), .PRE(PRE), .Q(Q)) /* synthesis syn_noprune = 1 IOB = true */ ;
IBUF_LVDS pad_p (.I(I),  .O(I_w)) /* synthesis syn_noprune = 1 */ ;
IBUF_LVDS pad_n (.I(IB), .O(IB_w)) /* synthesis syn_noprune = 1 */ ;

endmodule // IBUFDS_FDPE_LVDS

module IBUFDS_FDR_LVDS (I,IB,C,R,Q);
input I, IB, C, R;
output Q;

wire I_w, IB_w /* synthesis syn_keep = 1 */ ;

FDR off_p (.D(I_w), .C(C), .R(R), .Q(Q)) /* synthesis syn_noprune = 1 IOB = true */ ;
IBUF_LVDS pad_p (.I(I),  .O(I_w)) /* synthesis syn_noprune = 1 */ ;
IBUF_LVDS pad_n (.I(IB), .O(IB_w)) /* synthesis syn_noprune = 1 */ ;

endmodule // IBUFDS_FDR_LVDS

module IBUFDS_FDRE_LVDS (I,IB,CE,C,R,Q);
input I, IB, CE, C, R;
output Q;

wire I_w, IB_w /* synthesis syn_keep = 1 */ ;

FDRE off_p (.D(I_w),   .CE(CE), .C(C), .R(R), .Q(Q)) /* synthesis syn_noprune = 1 IOB = true */ ;
IBUF_LVDS pad_p (.I(I),  .O(I_w)) /* synthesis syn_noprune = 1 */ ;
IBUF_LVDS pad_n (.I(IB), .O(IB_w)) /* synthesis syn_noprune = 1 */ ;

endmodule // IBUFDS_FDRE_LVDS

module IBUFDS_FDS_LVDS (I,IB,C,S,Q);
input I, IB, C, S;
output Q;

wire I_w, IB_w /* synthesis syn_keep = 1 */ ;

FDS off_p (.D(I_w), .C(C), .S(S), .Q(Q)) /* synthesis syn_noprune = 1 IOB = true */ ;
IBUF_LVDS pad_p (.I(I),  .O(I_w)) /* synthesis syn_noprune = 1 */ ;
IBUF_LVDS pad_n (.I(IB), .O(IB_w)) /* synthesis syn_noprune = 1 */ ;

endmodule // IBUFDS_FDS_LVDS

module IBUFDS_FDSE_LVDS (I,IB,CE,C,S,Q);
input I, IB, CE, C, S;
output Q;

wire I_w, IB_w /* synthesis syn_keep = 1 */ ;

FDSE off_p (.D(I_w),   .CE(CE), .C(C), .S(S), .Q(Q)) /* synthesis syn_noprune = 1 IOB = true */ ;
IBUF_LVDS pad_p (.I(I),  .O(I_w)) /* synthesis syn_noprune = 1 */ ;
IBUF_LVDS pad_n (.I(IB), .O(IB_w)) /* synthesis syn_noprune = 1 */ ;

endmodule // IBUFDS_FDSE_LVDS

// *************
// Input Latches
// *************
module IBUFDS_LD_LVDS (I,IB,G,Q);
input I, IB, G;
output Q;

wire I_w, IB_w /* synthesis syn_keep = 1 */ ;

LD olatch_p (.D(I_w), .G(G), .Q(Q)) /* synthesis syn_noprune = 1 IOB = true */ ;
IBUF_LVDS pad_p (.I(I),  .O(I_w)) /* synthesis syn_noprune = 1 */ ;
IBUF_LVDS pad_n (.I(IB), .O(IB_w)) /* synthesis syn_noprune = 1 */ ;

endmodule // IBUFDS_LD_LVDS

module IBUFDS_LDE_LVDS (I,IB,GE,G,Q);
input I, IB, GE, G;
output Q;

wire I_w, IB_w /* synthesis syn_keep = 1 */ ;

LDE olatch_p (.D(I_w), .GE(GE), .G(G), .Q(Q)) /* synthesis syn_noprune = 1 IOB = true */ ;
IBUF_LVDS pad_p (.I(I),  .O(I_w)) /* synthesis syn_noprune = 1 */ ;
IBUF_LVDS pad_n (.I(IB), .O(IB_w)) /* synthesis syn_noprune = 1 */ ;

endmodule // IBUFDS_LDE_LVDS 

module IBUFDS_LDC_LVDS (I,IB,G,CLR,Q);
input I, IB, G, CLR;
output Q;

wire I_w, IB_w /* synthesis syn_keep = 1 */ ;

LDC olatch_p (.D(I_w), .G(G), .CLR(CLR), .Q(Q)) /* synthesis syn_noprune = 1 IOB = true */ ;
IBUF_LVDS pad_p (.I(I),  .O(I_w)) /* synthesis syn_noprune = 1 */ ;
IBUF_LVDS pad_n (.I(IB), .O(IB_w)) /* synthesis syn_noprune = 1 */ ;

endmodule // IBUFDS_LDC_LVDS 

module IBUFDS_LDCE_LVDS (I,IB,GE,G,CLR,Q);
input I, IB, GE, G, CLR;
output Q;

wire I_w, IB_w /* synthesis syn_keep = 1 */ ;

LDCE olatch_p (.D(I_w), .GE(GE), .G(G), .CLR(CLR), .Q(Q)) /* synthesis syn_noprune = 1 IOB = true */ ;
IBUF_LVDS pad_p (.I(I),  .O(I_w)) /* synthesis syn_noprune = 1 */ ;
IBUF_LVDS pad_n (.I(IB), .O(IB_w)) /* synthesis syn_noprune = 1 */ ;

endmodule // IBUFDS_LDCE_LVDS

module IBUFDS_LDP_LVDS (I,IB,G,PRE,Q);
input I, IB, G, PRE;
output Q;

wire I_w, IB_w /* synthesis syn_keep = 1 */ ;

LDP olatch_p (.D(I_w), .G(G), .PRE(PRE), .Q(Q)) /* synthesis syn_noprune = 1 IOB = true */ ;
IBUF_LVDS pad_p (.I(I),  .O(I_w)) /* synthesis syn_noprune = 1 */ ;
IBUF_LVDS pad_n (.I(IB), .O(IB_w)) /* synthesis syn_noprune = 1 */ ;

endmodule // IBUFDS_LDP_LVDS

module IBUFDS_LDPE_LVDS (I,IB,GE,G,PRE,Q);
input I, IB, GE, G, PRE;
output Q;

wire I_w, IB_w /* synthesis syn_keep = 1 */ ;

LDPE olatch_p (.D(I_w),   .GE(GE), .G(G), .PRE(PRE), .Q(Q)) /* synthesis syn_noprune = 1 IOB = true */ ;
IBUF_LVDS pad_p (.I(I),  .O(I_w)) /* synthesis syn_noprune = 1 */ ;
IBUF_LVDS pad_n (.I(IB), .O(IB_w)) /* synthesis syn_noprune = 1 */ ;

endmodule // IBUFDS_LDPE_LVDS

// ***************************
// Start of the Output Buffers
// Output Flipflops
// ***************************

module OBUFDS_FD_LVDS (D,C,O,OB);
input D, C;
output O,OB;

wire D_n,q_p,q_n /* synthesis syn_keep = 1 */ ;
wire CLR = 0; // Used to ensure that p and n are opposite on reset

INV  inv_n (.I(D), .O(D_n)) /* synthesis syn_noprune = 1 */ ;
FDC off_p (.D(D), .C(C), .CLR(CLR), .Q(q_p)) /* synthesis syn_noprune = 1 IOB = true */ ;
FDP off_n (.D(D_n), .C(C), .PRE(CLR), .Q(q_n)) /* synthesis syn_noprune = 1 IOB = true */ ;
OBUF_LVDS pad_p (.I(q_p), .O(O)) /* synthesis syn_noprune = 1 */ ;
OBUF_LVDS pad_n (.I(q_n), .O(OB)) /* synthesis syn_noprune = 1 */ ;

endmodule // OBUFDS_FD_LVDS

module OBUFDS_FDE_LVDS (D,CE,C,O,OB);
input D, CE, C;
output O,OB;

wire D_n,q_p,q_n /* synthesis syn_keep = 1 */ ;
wire CLR = 0; // Used to ensure that p and n are opposite on reset

INV  inv_n (.I(D), .O(D_n)) /* synthesis syn_noprune = 1 */ ;
FDCE off_p (.D(D),   .CE(CE), .C(C), .CLR(CLR), .Q(q_p)) /* synthesis syn_noprune = 1 IOB = true */ ;
FDPE off_n (.D(D_n), .CE(CE), .C(C), .PRE(CLR), .Q(q_n)) /* synthesis syn_noprune = 1 IOB = true */ ;
OBUF_LVDS pad_p (.I(q_p), .O(O)) /* synthesis syn_noprune = 1 */ ;
OBUF_LVDS pad_n (.I(q_n), .O(OB)) /* synthesis syn_noprune = 1 */ ;

endmodule // OBUFDS_FDE_LVDS

module OBUFDS_FDC_LVDS (D,C,CLR,O,OB);
input D, C, CLR;
output O,OB;

wire D_n,q_p,q_n /* synthesis syn_keep = 1 */ ;

INV  inv_n (.I(D), .O(D_n)) /* synthesis syn_noprune = 1 */ ;
FDC off_p (.D(D),   .C(C), .CLR(CLR), .Q(q_p)) /* synthesis syn_noprune = 1 IOB = true */ ;
FDP off_n (.D(D_n), .C(C), .PRE(CLR), .Q(q_n)) /* synthesis syn_noprune = 1 IOB = true */ ;
OBUF_LVDS pad_p (.I(q_p), .O(O)) /* synthesis syn_noprune = 1 */ ;
OBUF_LVDS pad_n (.I(q_n), .O(OB)) /* synthesis syn_noprune = 1 */ ;

endmodule // OBUFDS_FDC_LVDS

module OBUFDS_FDCE_LVDS (D,CE,C,CLR,O,OB);
input D, CE, C, CLR;
output O,OB;

wire D_n,q_p,q_n /* synthesis syn_keep = 1 */ ;

INV  inv_n (.I(D), .O(D_n)) /* synthesis syn_noprune = 1 */ ;
FDCE off_p (.D(D),   .CE(CE), .C(C), .CLR(CLR), .Q(q_p)) /* synthesis syn_noprune = 1 IOB = true */ ;
FDPE off_n (.D(D_n), .CE(CE), .C(C), .PRE(CLR), .Q(q_n)) /* synthesis syn_noprune = 1 IOB = true */ ;
OBUF_LVDS pad_p (.I(q_p), .O(O)) /* synthesis syn_noprune = 1 */ ;
OBUF_LVDS pad_n (.I(q_n), .O(OB)) /* synthesis syn_noprune = 1 */ ;

endmodule // OBUFDS_FDCE_LVDS

module OBUFDS_FDP_LVDS (D,C,PRE,O,OB);
input D, C, PRE;
output O,OB;

wire D_n,q_p,q_n /* synthesis syn_keep = 1 */ ;

INV  inv_n (.I(D), .O(D_n)) /* synthesis syn_noprune = 1 */ ;
FDP off_p (.D(D),   .C(C), .PRE(PRE), .Q(q_p)) /* synthesis syn_noprune = 1 IOB = true */ ;
FDC off_n (.D(D_n), .C(C), .CLR(PRE), .Q(q_n)) /* synthesis syn_noprune = 1 IOB = true */ ;
OBUF_LVDS pad_p (.I(q_p), .O(O)) /* synthesis syn_noprune = 1 */ ;
OBUF_LVDS pad_n (.I(q_n), .O(OB)) /* synthesis syn_noprune = 1 */ ;

endmodule // OBUFDS_FDP_LVDS

module OBUFDS_FDPE_LVDS (D,CE,C,PRE,O,OB);
input D, CE, C, PRE;
output O,OB;

wire D_n,q_p,q_n /* synthesis syn_keep = 1 */ ;

INV  inv_n (.I(D), .O(D_n)) /* synthesis syn_noprune = 1 */ ;
FDPE off_p (.D(D),   .CE(CE), .C(C), .PRE(PRE), .Q(q_p)) /* synthesis syn_noprune = 1 IOB = true */ ;
FDCE off_n (.D(D_n), .CE(CE), .C(C), .CLR(PRE), .Q(q_n)) /* synthesis syn_noprune = 1 IOB = true */ ;
OBUF_LVDS pad_p (.I(q_p), .O(O)) /* synthesis syn_noprune = 1 */ ;
OBUF_LVDS pad_n (.I(q_n), .O(OB)) /* synthesis syn_noprune = 1 */ ;

endmodule // OBUFDS_FDPE_LVDS

module OBUFDS_FDR_LVDS (D,C,R,O,OB);
input D, C, R;
output O,OB;

wire D_n,q_p,q_n /* synthesis syn_keep = 1 */ ;

INV  inv_n (.I(D), .O(D_n)) /* synthesis syn_noprune = 1 */ ;
FDR off_p (.D(D),   .C(C), .R(R), .Q(q_p)) /* synthesis syn_noprune = 1 IOB = true */ ;
FDS off_n (.D(D_n), .C(C), .S(R), .Q(q_n)) /* synthesis syn_noprune = 1 IOB = true */ ;
OBUF_LVDS pad_p (.I(q_p), .O(O)) /* synthesis syn_noprune = 1 */ ;
OBUF_LVDS pad_n (.I(q_n), .O(OB)) /* synthesis syn_noprune = 1 */ ;

endmodule // OBUFDS_FDR_LVDS

module OBUFDS_FDRE_LVDS (D,CE,C,R,O,OB);
input D, CE, C, R;
output O,OB;

wire D_n,q_p,q_n /* synthesis syn_keep = 1 */ ;

INV  inv_n (.I(D), .O(D_n)) /* synthesis syn_noprune = 1 */ ;
FDRE off_p (.D(D),   .CE(CE), .C(C), .R(R), .Q(q_p)) /* synthesis syn_noprune = 1 IOB = true */ ;
FDSE off_n (.D(D_n), .CE(CE), .C(C), .S(R), .Q(q_n)) /* synthesis syn_noprune = 1 IOB = true */ ;
OBUF_LVDS pad_p (.I(q_p), .O(O)) /* synthesis syn_noprune = 1 */ ;
OBUF_LVDS pad_n (.I(q_n), .O(OB)) /* synthesis syn_noprune = 1 */ ;

endmodule // OBUFDS_FDRE_LVDS

module OBUFDS_FDS_LVDS (D,C,S,O,OB);
input D, C, S;
output O,OB;

wire D_n,q_p,q_n /* synthesis syn_keep = 1 */ ;

INV  inv_n (.I(D), .O(D_n)) /* synthesis syn_noprune = 1 */ ;
FDS off_p (.D(D),   .C(C), .S(S), .Q(q_p)) /* synthesis syn_noprune = 1 IOB = true */ ;
FDR off_n (.D(D_n), .C(C), .R(S), .Q(q_n)) /* synthesis syn_noprune = 1 IOB = true */ ;
OBUF_LVDS pad_p (.I(q_p), .O(O)) /* synthesis syn_noprune = 1 */ ;
OBUF_LVDS pad_n (.I(q_n), .O(OB)) /* synthesis syn_noprune = 1 */ ;

endmodule // OBUFDS_FDS_LVDS

module OBUFDS_FDSE_LVDS (D,CE,C,S,O,OB);
input D, CE, C, S;
output O,OB;

wire D_n,q_p,q_n /* synthesis syn_keep = 1 */ ;

INV  inv_n (.I(D), .O(D_n)) /* synthesis syn_noprune = 1 */ ;